Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7542995 [patent_doc_number] => 08060844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Method for generating optimized constraint systems for retimable digital designs' [patent_app_type] => utility [patent_app_number] => 12/324742 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4471 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/060/08060844.pdf [firstpage_image] =>[orig_patent_app_number] => 12324742 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/324742
Method for generating optimized constraint systems for retimable digital designs Nov 25, 2008 Issued
Array ( [id] => 5273744 [patent_doc_number] => 20090077520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Method and System for Representing Manufacturing and Lithography Information for IC Routing' [patent_app_type] => utility [patent_app_number] => 12/276263 [patent_app_country] => US [patent_app_date] => 2008-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4400 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077520.pdf [firstpage_image] =>[orig_patent_app_number] => 12276263 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/276263
Method and system for representing manufacturing and lithography information for IC routing Nov 20, 2008 Issued
Array ( [id] => 5273745 [patent_doc_number] => 20090077521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Method and System for Representing Manufacturing and Lithography Information for IC Routing' [patent_app_type] => utility [patent_app_number] => 12/276267 [patent_app_country] => US [patent_app_date] => 2008-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4400 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077521.pdf [firstpage_image] =>[orig_patent_app_number] => 12276267 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/276267
Method and system for representing manufacturing and lithography information for IC routing Nov 20, 2008 Issued
Array ( [id] => 5326081 [patent_doc_number] => 20090064071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'METHOD AND SYSTEM FOR GLOBAL COVERAGE ANALYSIS' [patent_app_type] => utility [patent_app_number] => 12/267779 [patent_app_country] => US [patent_app_date] => 2008-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5005 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20090064071.pdf [firstpage_image] =>[orig_patent_app_number] => 12267779 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/267779
METHOD AND SYSTEM FOR GLOBAL COVERAGE ANALYSIS Nov 9, 2008 Abandoned
Array ( [id] => 8149412 [patent_doc_number] => 08166429 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-24 [patent_title] => 'Multi-layer distributed network' [patent_app_type] => utility [patent_app_number] => 12/253910 [patent_app_country] => US [patent_app_date] => 2008-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3182 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/166/08166429.pdf [firstpage_image] =>[orig_patent_app_number] => 12253910 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/253910
Multi-layer distributed network Oct 16, 2008 Issued
Array ( [id] => 5273741 [patent_doc_number] => 20090077517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Semiconductor intergrated device and apparatus for designing the same' [patent_app_type] => utility [patent_app_number] => 12/288084 [patent_app_country] => US [patent_app_date] => 2008-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8865 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077517.pdf [firstpage_image] =>[orig_patent_app_number] => 12288084 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/288084
Semiconductor integrated device and apparatus for designing the same Oct 15, 2008 Issued
Array ( [id] => 5273740 [patent_doc_number] => 20090077516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Semiconductor integrated device and apparatus for designing the same' [patent_app_type] => utility [patent_app_number] => 12/288083 [patent_app_country] => US [patent_app_date] => 2008-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8801 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20090077516.pdf [firstpage_image] =>[orig_patent_app_number] => 12288083 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/288083
Semiconductor integrated device and apparatus for designing the same Oct 15, 2008 Issued
Array ( [id] => 325419 [patent_doc_number] => 07519931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-14 [patent_title] => 'Applying CNF simplification techniques for SAT-based abstraction refinement' [patent_app_type] => utility [patent_app_number] => 12/250534 [patent_app_country] => US [patent_app_date] => 2008-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2179 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/519/07519931.pdf [firstpage_image] =>[orig_patent_app_number] => 12250534 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/250534
Applying CNF simplification techniques for SAT-based abstraction refinement Oct 12, 2008 Issued
Array ( [id] => 5430410 [patent_doc_number] => 20090089720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'METHOD AND MECHANISM FOR IDENTIFYING AND TRACKING SHAPE CONNECTIVITY' [patent_app_type] => utility [patent_app_number] => 12/242356 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 18627 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20090089720.pdf [firstpage_image] =>[orig_patent_app_number] => 12242356 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/242356
Method and mechanism for identifying and tracking shape connectivity Sep 29, 2008 Issued
Array ( [id] => 6389478 [patent_doc_number] => 20100083194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'SYSTEM AND METHOD FOR FINDING CONNECTED COMPONENTS IN A LARGE-SCALE GRAPH' [patent_app_type] => utility [patent_app_number] => 12/239770 [patent_app_country] => US [patent_app_date] => 2008-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20100083194.pdf [firstpage_image] =>[orig_patent_app_number] => 12239770 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/239770
SYSTEM AND METHOD FOR FINDING CONNECTED COMPONENTS IN A LARGE-SCALE GRAPH Sep 26, 2008 Abandoned
Array ( [id] => 8331721 [patent_doc_number] => 08239797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-07 [patent_title] => 'Congestion aware block placement' [patent_app_type] => utility [patent_app_number] => 12/233460 [patent_app_country] => US [patent_app_date] => 2008-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 4690 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12233460 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/233460
Congestion aware block placement Sep 17, 2008 Issued
Array ( [id] => 7557514 [patent_doc_number] => 08069424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'Generating a base curve database to reduce storage cost' [patent_app_type] => utility [patent_app_number] => 12/212606 [patent_app_country] => US [patent_app_date] => 2008-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4978 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/069/08069424.pdf [firstpage_image] =>[orig_patent_app_number] => 12212606 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/212606
Generating a base curve database to reduce storage cost Sep 16, 2008 Issued
Array ( [id] => 5298374 [patent_doc_number] => 20090013300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'SYNTHESIS STRATEGIES BASED ON THE APPROPRIATE USE OF INDUCTANCE EFFECTS' [patent_app_type] => utility [patent_app_number] => 12/210915 [patent_app_country] => US [patent_app_date] => 2008-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11080 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20090013300.pdf [firstpage_image] =>[orig_patent_app_number] => 12210915 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/210915
Synthesis strategies based on the appropriate use of inductance effects Sep 14, 2008 Issued
Array ( [id] => 8273262 [patent_doc_number] => 08214781 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-03 [patent_title] => 'Empirical prediction of simultaneous switching noise' [patent_app_type] => utility [patent_app_number] => 12/208190 [patent_app_country] => US [patent_app_date] => 2008-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4557 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12208190 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/208190
Empirical prediction of simultaneous switching noise Sep 9, 2008 Issued
Array ( [id] => 4854680 [patent_doc_number] => 20080320424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'VALIDATION OF ELECTRICAL PERFORMANCE OF AN ELECTRONIC PACKAGE PRIOR TO FABRICATION' [patent_app_type] => utility [patent_app_number] => 12/203955 [patent_app_country] => US [patent_app_date] => 2008-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20080320424.pdf [firstpage_image] =>[orig_patent_app_number] => 12203955 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/203955
Validation of electrical performance of an electronic package prior to fabrication Sep 3, 2008 Issued
Array ( [id] => 8319805 [patent_doc_number] => 08234604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Co-optimization of embedded systems utilizing symbolic execution' [patent_app_type] => utility [patent_app_number] => 12/202500 [patent_app_country] => US [patent_app_date] => 2008-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6106 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12202500 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/202500
Co-optimization of embedded systems utilizing symbolic execution Sep 1, 2008 Issued
Array ( [id] => 8273260 [patent_doc_number] => 08214780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Optimization of verification of chip design' [patent_app_type] => utility [patent_app_number] => 12/199790 [patent_app_country] => US [patent_app_date] => 2008-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5755 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12199790 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/199790
Optimization of verification of chip design Aug 26, 2008 Issued
Array ( [id] => 7780235 [patent_doc_number] => 08122396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-02-21 [patent_title] => 'Local searching techniques for technology mapping' [patent_app_type] => utility [patent_app_number] => 12/198428 [patent_app_country] => US [patent_app_date] => 2008-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5904 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/122/08122396.pdf [firstpage_image] =>[orig_patent_app_number] => 12198428 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/198428
Local searching techniques for technology mapping Aug 25, 2008 Issued
Array ( [id] => 9630143 [patent_doc_number] => 08799837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Optimizing a netlist circuit representation by leveraging binary decision diagrams to perform rewriting' [patent_app_type] => utility [patent_app_number] => 12/197980 [patent_app_country] => US [patent_app_date] => 2008-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6423 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12197980 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/197980
Optimizing a netlist circuit representation by leveraging binary decision diagrams to perform rewriting Aug 24, 2008 Issued
Array ( [id] => 7803849 [patent_doc_number] => 08132133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-06 [patent_title] => 'Automated isolation of logic and macro blocks in chip design testing' [patent_app_type] => utility [patent_app_number] => 12/196840 [patent_app_country] => US [patent_app_date] => 2008-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4990 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/132/08132133.pdf [firstpage_image] =>[orig_patent_app_number] => 12196840 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/196840
Automated isolation of logic and macro blocks in chip design testing Aug 21, 2008 Issued
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