Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7768448 [patent_doc_number] => 08117573 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Verification-scenario generating apparatus, verification-scenario generating method, and computer product' [patent_app_type] => utility [patent_app_number] => 12/230110 [patent_app_country] => US [patent_app_date] => 2008-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8257 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/117/08117573.pdf [firstpage_image] =>[orig_patent_app_number] => 12230110 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/230110
Verification-scenario generating apparatus, verification-scenario generating method, and computer product Aug 21, 2008 Issued
Array ( [id] => 6619487 [patent_doc_number] => 20100050139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'DATA PROCESSING DEVICE DESIGN TOOL AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/196730 [patent_app_country] => US [patent_app_date] => 2008-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4775 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20100050139.pdf [firstpage_image] =>[orig_patent_app_number] => 12196730 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/196730
Data processing device design tool and methods Aug 21, 2008 Issued
Array ( [id] => 5448194 [patent_doc_number] => 20090049420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'Dummy pattern placement apparatus, method and program and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/222600 [patent_app_country] => US [patent_app_date] => 2008-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7166 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20090049420.pdf [firstpage_image] =>[orig_patent_app_number] => 12222600 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/222600
Dummy pattern placement apparatus, method and program and semiconductor device Aug 11, 2008 Issued
Array ( [id] => 4794070 [patent_doc_number] => 20080295044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'METHOD AND APPARATUS FOR MAPPING DESIGN MEMORIES TO INTEGRATED CIRCUIT LAYOUT' [patent_app_type] => utility [patent_app_number] => 12/186159 [patent_app_country] => US [patent_app_date] => 2008-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6723 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0295/20080295044.pdf [firstpage_image] =>[orig_patent_app_number] => 12186159 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/186159
Method and apparatus for mapping design memories to integrated circuit layout Aug 4, 2008 Issued
Array ( [id] => 8861644 [patent_doc_number] => 08464198 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-11 [patent_title] => 'Electronic design automation tool and method for employing unsensitized critical path information to reduce leakage power in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/182330 [patent_app_country] => US [patent_app_date] => 2008-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3653 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12182330 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/182330
Electronic design automation tool and method for employing unsensitized critical path information to reduce leakage power in an integrated circuit Jul 29, 2008 Issued
Array ( [id] => 5358603 [patent_doc_number] => 20090033397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Delay time adjusting method of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/219840 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3408 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20090033397.pdf [firstpage_image] =>[orig_patent_app_number] => 12219840 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219840
Delay time adjusting method of semiconductor integrated circuit Jul 28, 2008 Issued
Array ( [id] => 4621773 [patent_doc_number] => 08001504 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-16 [patent_title] => 'Determining clock skew between nodes of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/181350 [patent_app_country] => US [patent_app_date] => 2008-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/001/08001504.pdf [firstpage_image] =>[orig_patent_app_number] => 12181350 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/181350
Determining clock skew between nodes of an integrated circuit Jul 28, 2008 Issued
Array ( [id] => 8235652 [patent_doc_number] => 08201113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Method and apparatus for multi-die thermal analysis' [patent_app_type] => utility [patent_app_number] => 12/180490 [patent_app_country] => US [patent_app_date] => 2008-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/201/08201113.pdf [firstpage_image] =>[orig_patent_app_number] => 12180490 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/180490
Method and apparatus for multi-die thermal analysis Jul 24, 2008 Issued
Array ( [id] => 9630144 [patent_doc_number] => 08799839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-05 [patent_title] => 'Extraction tool and method for determining maximum and minimum stage delays associated with integrated circuit interconnects' [patent_app_type] => utility [patent_app_number] => 12/179070 [patent_app_country] => US [patent_app_date] => 2008-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12179070 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/179070
Extraction tool and method for determining maximum and minimum stage delays associated with integrated circuit interconnects Jul 23, 2008 Issued
Array ( [id] => 7746672 [patent_doc_number] => 08108809 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-31 [patent_title] => 'Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/219371 [patent_app_country] => US [patent_app_date] => 2008-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7771 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/108/08108809.pdf [firstpage_image] =>[orig_patent_app_number] => 12219371 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/219371
Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit Jul 20, 2008 Issued
Array ( [id] => 6566351 [patent_doc_number] => 20100017764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'FUNCTIONAL VERIFICATION OF POWER GATED DESIGNS BY COMPOSITIONAL REASONING' [patent_app_type] => utility [patent_app_number] => 12/174650 [patent_app_country] => US [patent_app_date] => 2008-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5920 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20100017764.pdf [firstpage_image] =>[orig_patent_app_number] => 12174650 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/174650
Functional verification of power gated designs by compositional reasoning Jul 16, 2008 Issued
Array ( [id] => 10021580 [patent_doc_number] => 09064068 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-23 [patent_title] => 'Debuggable opaque IP' [patent_app_type] => utility [patent_app_number] => 12/168697 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7176 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12168697 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/168697
Debuggable opaque IP Jul 6, 2008 Issued
Array ( [id] => 7706520 [patent_doc_number] => 08091049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-03 [patent_title] => 'Integrated single spice deck sensitization for gate level tools' [patent_app_type] => utility [patent_app_number] => 12/166630 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4443 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/091/08091049.pdf [firstpage_image] =>[orig_patent_app_number] => 12166630 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166630
Integrated single spice deck sensitization for gate level tools Jul 1, 2008 Issued
Array ( [id] => 9289536 [patent_doc_number] => 08645894 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-02-04 [patent_title] => 'Configuration and analysis of design variants of multi-domain circuits' [patent_app_type] => utility [patent_app_number] => 12/166730 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 10514 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12166730 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166730
Configuration and analysis of design variants of multi-domain circuits Jul 1, 2008 Issued
Array ( [id] => 8319816 [patent_doc_number] => 08234611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'System and method for modeling I/O simultaneous switching noise' [patent_app_type] => utility [patent_app_number] => 12/166550 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4361 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12166550 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/166550
System and method for modeling I/O simultaneous switching noise Jul 1, 2008 Issued
Array ( [id] => 4961791 [patent_doc_number] => 20080276216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Pattern forming method and system, and method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/216220 [patent_app_country] => US [patent_app_date] => 2008-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8621 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20080276216.pdf [firstpage_image] =>[orig_patent_app_number] => 12216220 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/216220
Pattern forming method and system, and method of manufacturing a semiconductor device Jun 30, 2008 Issued
Array ( [id] => 5462211 [patent_doc_number] => 20090322411 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'CIRCUIT AND METHOD FOR AVOIDING SOFT ERRORS IN STORAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 12/164760 [patent_app_country] => US [patent_app_date] => 2008-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0322/20090322411.pdf [firstpage_image] =>[orig_patent_app_number] => 12164760 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/164760
Circuit and method for avoiding soft errors in storage devices Jun 29, 2008 Issued
Array ( [id] => 9169964 [patent_doc_number] => 08595658 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Clock signal networks for structured ASIC devices' [patent_app_type] => utility [patent_app_number] => 12/147200 [patent_app_country] => US [patent_app_date] => 2008-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3893 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12147200 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/147200
Clock signal networks for structured ASIC devices Jun 25, 2008 Issued
Array ( [id] => 7542994 [patent_doc_number] => 08060843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Verification of 3D integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/141690 [patent_app_country] => US [patent_app_date] => 2008-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6877 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/060/08060843.pdf [firstpage_image] =>[orig_patent_app_number] => 12141690 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/141690
Verification of 3D integrated circuits Jun 17, 2008 Issued
Array ( [id] => 8235672 [patent_doc_number] => 08201133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Printed circuit board with reduced signal distortion' [patent_app_type] => utility [patent_app_number] => 12/140730 [patent_app_country] => US [patent_app_date] => 2008-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4204 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/201/08201133.pdf [firstpage_image] =>[orig_patent_app_number] => 12140730 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/140730
Printed circuit board with reduced signal distortion Jun 16, 2008 Issued
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