
Paul Dinh
Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2816, 2825 |
| Total Applications | 2030 |
| Issued Applications | 1783 |
| Pending Applications | 89 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4684136
[patent_doc_number] => 20080250362
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-09
[patent_title] => 'Method and System Product for Implementing Uncertainty in Integrated Circuit Designs with Programmable Logic'
[patent_app_type] => utility
[patent_app_number] => 12/137628
[patent_app_country] => US
[patent_app_date] => 2008-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0250/20080250362.pdf
[firstpage_image] =>[orig_patent_app_number] => 12137628
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/137628 | Method and system product for implementing uncertainty in integrated circuit designs with programmable logic | Jun 11, 2008 | Issued |
Array
(
[id] => 7553297
[patent_doc_number] => 08065639
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-22
[patent_title] => 'Semiconductor integrated circuit designing method'
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[firstpage_image] =>[orig_patent_app_number] => 12136230
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/136230 | Semiconductor integrated circuit designing method | Jun 9, 2008 | Issued |
Array
(
[id] => 5370078
[patent_doc_number] => 20090307637
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-10
[patent_title] => 'METHOD OF DESIGNING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK'
[patent_app_type] => utility
[patent_app_number] => 12/135250
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 12135250
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/135250 | Method of designing multi-state restore circuitry for restoring state to a power managed functional block | Jun 8, 2008 | Issued |
Array
(
[id] => 5370077
[patent_doc_number] => 20090307636
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-10
[patent_title] => 'SOLUTION EFFICIENCY OF GENETIC ALGORITHM APPLICATIONS'
[patent_app_type] => utility
[patent_app_number] => 12/133480
[patent_app_country] => US
[patent_app_date] => 2008-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/133480 | SOLUTION EFFICIENCY OF GENETIC ALGORITHM APPLICATIONS | Jun 4, 2008 | Abandoned |
Array
(
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[patent_doc_number] => 20080235635
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[patent_kind] => A1
[patent_issue_date] => 2008-09-25
[patent_title] => 'SYSTEM ON CHIP DEVELOPMENT WITH RECONFIGURABLE MULTI-PROJECT WAFER TECHNOLOGY'
[patent_app_type] => utility
[patent_app_number] => 12/133323
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/133323 | System on chip development with reconfigurable multi-project wafer technology | Jun 3, 2008 | Issued |
Array
(
[id] => 8170968
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[patent_kind] => B2
[patent_issue_date] => 2012-05-08
[patent_title] => 'Layout of printable assist features to aid transistor control'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/131370 | Layout of printable assist features to aid transistor control | Jun 1, 2008 | Issued |
Array
(
[id] => 5280839
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[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-05-21
[patent_title] => 'Structure for a Circuit Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler'
[patent_app_type] => utility
[patent_app_number] => 12/130040
[patent_app_country] => US
[patent_app_date] => 2008-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[firstpage_image] =>[orig_patent_app_number] => 12130040
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/130040 | Structure for a circuit obtaining desired phase locked loop duty cycle without pre-scaler | May 29, 2008 | Issued |
Array
(
[id] => 7495212
[patent_doc_number] => 08032849
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-10-04
[patent_title] => 'Integrated circuit chip with modular design'
[patent_app_type] => utility
[patent_app_number] => 12/130268
[patent_app_country] => US
[patent_app_date] => 2008-05-30
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[firstpage_image] =>[orig_patent_app_number] => 12130268
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/130268 | Integrated circuit chip with modular design | May 29, 2008 | Issued |
Array
(
[id] => 4528405
[patent_doc_number] => 07934181
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[patent_kind] => B2
[patent_issue_date] => 2011-04-26
[patent_title] => 'Method and apparatus for improving SRAM cell stability by using boosted word lines'
[patent_app_type] => utility
[patent_app_number] => 12/130472
[patent_app_country] => US
[patent_app_date] => 2008-05-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/130472 | Method and apparatus for improving SRAM cell stability by using boosted word lines | May 29, 2008 | Issued |
Array
(
[id] => 8799632
[patent_doc_number] => 08438521
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[patent_issue_date] => 2013-05-07
[patent_title] => 'Methods and apparatus for implementing application specific processors'
[patent_app_type] => utility
[patent_app_number] => 12/130679
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/130679 | Methods and apparatus for implementing application specific processors | May 29, 2008 | Issued |
Array
(
[id] => 4713070
[patent_doc_number] => 20080301596
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[patent_kind] => A1
[patent_issue_date] => 2008-12-04
[patent_title] => 'Method and System for Testing Bit Failures in Array Elements of an Electronic Circuit'
[patent_app_type] => utility
[patent_app_number] => 12/127900
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[patent_app_date] => 2008-05-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/127900 | Method and system for testing bit failures in array elements of an electronic circuit | May 27, 2008 | Issued |
Array
(
[id] => 5351688
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[patent_title] => 'AUTOMATIC TRACE DESIGN METHOD'
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Array
(
[id] => 7537752
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[patent_title] => 'Method of labelling swappable pins for integrated circuit pattern matching'
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Array
(
[id] => 4780909
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/149910 | Method of verifying semiconductor integrated circuit and design program | May 8, 2008 | Issued |
Array
(
[id] => 4678404
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[patent_issue_date] => 2008-09-04
[patent_title] => 'METHOD AND COMPUTER PROGRAM FOR CONFIGURING AN INTEGRATED CIRCUIT DESIGN FOR STATIC TIMING ANALYSIS'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/117760 | Method and computer program for configuring an integrated circuit design for static timing analysis | May 8, 2008 | Issued |
Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/114530 | System and method for process rules editors | May 1, 2008 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/113200 | Method and apparatus for configurable systems | Apr 29, 2008 | Issued |