Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4684136 [patent_doc_number] => 20080250362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Method and System Product for Implementing Uncertainty in Integrated Circuit Designs with Programmable Logic' [patent_app_type] => utility [patent_app_number] => 12/137628 [patent_app_country] => US [patent_app_date] => 2008-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4622 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250362.pdf [firstpage_image] =>[orig_patent_app_number] => 12137628 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/137628
Method and system product for implementing uncertainty in integrated circuit designs with programmable logic Jun 11, 2008 Issued
Array ( [id] => 7553297 [patent_doc_number] => 08065639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Semiconductor integrated circuit designing method' [patent_app_type] => utility [patent_app_number] => 12/136230 [patent_app_country] => US [patent_app_date] => 2008-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 7676 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/065/08065639.pdf [firstpage_image] =>[orig_patent_app_number] => 12136230 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/136230
Semiconductor integrated circuit designing method Jun 9, 2008 Issued
Array ( [id] => 5370078 [patent_doc_number] => 20090307637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'METHOD OF DESIGNING MULTI-STATE RESTORE CIRCUITRY FOR RESTORING STATE TO A POWER-MANAGED FUNCTIONAL BLOCK' [patent_app_type] => utility [patent_app_number] => 12/135250 [patent_app_country] => US [patent_app_date] => 2008-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20090307637.pdf [firstpage_image] =>[orig_patent_app_number] => 12135250 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/135250
Method of designing multi-state restore circuitry for restoring state to a power managed functional block Jun 8, 2008 Issued
Array ( [id] => 5370077 [patent_doc_number] => 20090307636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'SOLUTION EFFICIENCY OF GENETIC ALGORITHM APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 12/133480 [patent_app_country] => US [patent_app_date] => 2008-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4447 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20090307636.pdf [firstpage_image] =>[orig_patent_app_number] => 12133480 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/133480
SOLUTION EFFICIENCY OF GENETIC ALGORITHM APPLICATIONS Jun 4, 2008 Abandoned
Array ( [id] => 4741982 [patent_doc_number] => 20080235635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'SYSTEM ON CHIP DEVELOPMENT WITH RECONFIGURABLE MULTI-PROJECT WAFER TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 12/133323 [patent_app_country] => US [patent_app_date] => 2008-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2768 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235635.pdf [firstpage_image] =>[orig_patent_app_number] => 12133323 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/133323
System on chip development with reconfigurable multi-project wafer technology Jun 3, 2008 Issued
Array ( [id] => 8170968 [patent_doc_number] => 08176443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Layout of printable assist features to aid transistor control' [patent_app_type] => utility [patent_app_number] => 12/131370 [patent_app_country] => US [patent_app_date] => 2008-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4276 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/176/08176443.pdf [firstpage_image] =>[orig_patent_app_number] => 12131370 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/131370
Layout of printable assist features to aid transistor control Jun 1, 2008 Issued
Array ( [id] => 5280839 [patent_doc_number] => 20090132971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'Structure for a Circuit Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler' [patent_app_type] => utility [patent_app_number] => 12/130040 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8084 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20090132971.pdf [firstpage_image] =>[orig_patent_app_number] => 12130040 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/130040
Structure for a circuit obtaining desired phase locked loop duty cycle without pre-scaler May 29, 2008 Issued
Array ( [id] => 7495212 [patent_doc_number] => 08032849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-04 [patent_title] => 'Integrated circuit chip with modular design' [patent_app_type] => utility [patent_app_number] => 12/130268 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2028 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/032/08032849.pdf [firstpage_image] =>[orig_patent_app_number] => 12130268 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/130268
Integrated circuit chip with modular design May 29, 2008 Issued
Array ( [id] => 4528405 [patent_doc_number] => 07934181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Method and apparatus for improving SRAM cell stability by using boosted word lines' [patent_app_type] => utility [patent_app_number] => 12/130472 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2783 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934181.pdf [firstpage_image] =>[orig_patent_app_number] => 12130472 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/130472
Method and apparatus for improving SRAM cell stability by using boosted word lines May 29, 2008 Issued
Array ( [id] => 8799632 [patent_doc_number] => 08438521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-07 [patent_title] => 'Methods and apparatus for implementing application specific processors' [patent_app_type] => utility [patent_app_number] => 12/130679 [patent_app_country] => US [patent_app_date] => 2008-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5964 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12130679 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/130679
Methods and apparatus for implementing application specific processors May 29, 2008 Issued
Array ( [id] => 4713070 [patent_doc_number] => 20080301596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Method and System for Testing Bit Failures in Array Elements of an Electronic Circuit' [patent_app_type] => utility [patent_app_number] => 12/127900 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3792 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0301/20080301596.pdf [firstpage_image] =>[orig_patent_app_number] => 12127900 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127900
Method and system for testing bit failures in array elements of an electronic circuit May 27, 2008 Issued
Array ( [id] => 5351688 [patent_doc_number] => 20090007049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'AUTOMATIC TRACE DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 12/127890 [patent_app_country] => US [patent_app_date] => 2008-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6577 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20090007049.pdf [firstpage_image] =>[orig_patent_app_number] => 12127890 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/127890
AUTOMATIC TRACE DESIGN METHOD May 27, 2008 Abandoned
Array ( [id] => 7537752 [patent_doc_number] => 08051395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-01 [patent_title] => 'Method of labelling swappable pins for integrated circuit pattern matching' [patent_app_type] => utility [patent_app_number] => 12/153320 [patent_app_country] => US [patent_app_date] => 2008-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4665 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/051/08051395.pdf [firstpage_image] =>[orig_patent_app_number] => 12153320 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/153320
Method of labelling swappable pins for integrated circuit pattern matching May 15, 2008 Issued
Array ( [id] => 4780909 [patent_doc_number] => 20080288908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'SIMULTANEOUS DESIGN OF INTEGRATED CIRCUIT AND PRINTED CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 12/121440 [patent_app_country] => US [patent_app_date] => 2008-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6344 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20080288908.pdf [firstpage_image] =>[orig_patent_app_number] => 12121440 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/121440
SIMULTANEOUS DESIGN OF INTEGRATED CIRCUIT AND PRINTED CIRCUIT BOARD May 14, 2008 Abandoned
Array ( [id] => 4761359 [patent_doc_number] => 20080313585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Method of verifying semiconductor integrated circuit and design program' [patent_app_type] => utility [patent_app_number] => 12/149910 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7918 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313585.pdf [firstpage_image] =>[orig_patent_app_number] => 12149910 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/149910
Method of verifying semiconductor integrated circuit and design program May 8, 2008 Issued
Array ( [id] => 4678404 [patent_doc_number] => 20080216035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'METHOD AND COMPUTER PROGRAM FOR CONFIGURING AN INTEGRATED CIRCUIT DESIGN FOR STATIC TIMING ANALYSIS' [patent_app_type] => utility [patent_app_number] => 12/117760 [patent_app_country] => US [patent_app_date] => 2008-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216035.pdf [firstpage_image] =>[orig_patent_app_number] => 12117760 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/117760
Method and computer program for configuring an integrated circuit design for static timing analysis May 8, 2008 Issued
Array ( [id] => 4447681 [patent_doc_number] => 07930655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Yield profile manipulator' [patent_app_type] => utility [patent_app_number] => 12/117379 [patent_app_country] => US [patent_app_date] => 2008-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3490 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930655.pdf [firstpage_image] =>[orig_patent_app_number] => 12117379 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/117379
Yield profile manipulator May 7, 2008 Issued
Array ( [id] => 4573948 [patent_doc_number] => 07962863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-14 [patent_title] => 'Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer' [patent_app_type] => utility [patent_app_number] => 12/115830 [patent_app_country] => US [patent_app_date] => 2008-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 9625 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/962/07962863.pdf [firstpage_image] =>[orig_patent_app_number] => 12115830 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/115830
Computer-implemented methods, systems, and computer-readable media for determining a model for predicting printability of reticle features on a wafer May 5, 2008 Issued
Array ( [id] => 8552416 [patent_doc_number] => 08327315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-04 [patent_title] => 'System and method for process rules editors' [patent_app_type] => utility [patent_app_number] => 12/114530 [patent_app_country] => US [patent_app_date] => 2008-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5543 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12114530 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/114530
System and method for process rules editors May 1, 2008 Issued
Array ( [id] => 4472738 [patent_doc_number] => 07937683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-03 [patent_title] => 'Method and apparatus for configurable systems' [patent_app_type] => utility [patent_app_number] => 12/113200 [patent_app_country] => US [patent_app_date] => 2008-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3073 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/937/07937683.pdf [firstpage_image] =>[orig_patent_app_number] => 12113200 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/113200
Method and apparatus for configurable systems Apr 29, 2008 Issued
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