Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4523193 [patent_doc_number] => 07917872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Simulation method and computer-readable storage medium' [patent_app_type] => utility [patent_app_number] => 12/111470 [patent_app_country] => US [patent_app_date] => 2008-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4726 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/917/07917872.pdf [firstpage_image] =>[orig_patent_app_number] => 12111470 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/111470
Simulation method and computer-readable storage medium Apr 28, 2008 Issued
Array ( [id] => 5560179 [patent_doc_number] => 20090271756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'Minimal Leakage-Power Standard Cell Library' [patent_app_type] => utility [patent_app_number] => 12/110170 [patent_app_country] => US [patent_app_date] => 2008-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3333 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20090271756.pdf [firstpage_image] =>[orig_patent_app_number] => 12110170 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/110170
Minimal leakage-power standard cell library Apr 24, 2008 Issued
Array ( [id] => 4859704 [patent_doc_number] => 20080268554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'FABRICATION METHOD FOR SEMICONDUCTOR DEVICE, EXPOSURE METHOD, PATTERN CORRECTION METHOD AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/108660 [patent_app_country] => US [patent_app_date] => 2008-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7215 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20080268554.pdf [firstpage_image] =>[orig_patent_app_number] => 12108660 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/108660
Fabrication method for semiconductor device, exposure method, pattern correction method and semiconductor device Apr 23, 2008 Issued
Array ( [id] => 4815353 [patent_doc_number] => 20080195984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'METHOD FOR OPTIMIZATION OF LOGIC CIRCUITS FOR ROUTABILITY IMPROVEMENT' [patent_app_type] => utility [patent_app_number] => 12/104852 [patent_app_country] => US [patent_app_date] => 2008-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20080195984.pdf [firstpage_image] =>[orig_patent_app_number] => 12104852 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/104852
METHOD FOR OPTIMIZATION OF LOGIC CIRCUITS FOR ROUTABILITY IMPROVEMENT Apr 16, 2008 Abandoned
Array ( [id] => 4715068 [patent_doc_number] => 20080237590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'DESIGN STRUCTURE FOR ELECTRICALLY TUNABLE RESISTOR' [patent_app_type] => utility [patent_app_number] => 12/100592 [patent_app_country] => US [patent_app_date] => 2008-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4124 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20080237590.pdf [firstpage_image] =>[orig_patent_app_number] => 12100592 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/100592
Structure for electrically tunable resistor Apr 9, 2008 Issued
Array ( [id] => 4602971 [patent_doc_number] => 07979816 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-12 [patent_title] => 'Method and apparatus for implementing a circuit design for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/100313 [patent_app_country] => US [patent_app_date] => 2008-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4276 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/979/07979816.pdf [firstpage_image] =>[orig_patent_app_number] => 12100313 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/100313
Method and apparatus for implementing a circuit design for an integrated circuit Apr 8, 2008 Issued
Array ( [id] => 4678416 [patent_doc_number] => 20080216047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Intermediate Layout for Resolution Enhancement in Semiconductor Fabrication' [patent_app_type] => utility [patent_app_number] => 12/099663 [patent_app_country] => US [patent_app_date] => 2008-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6264 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216047.pdf [firstpage_image] =>[orig_patent_app_number] => 12099663 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/099663
Intermediate layout for resolution enhancement in semiconductor fabrication Apr 7, 2008 Issued
Array ( [id] => 5454689 [patent_doc_number] => 20090070726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'Enhanced Routing Grid System and Method' [patent_app_type] => utility [patent_app_number] => 12/062360 [patent_app_country] => US [patent_app_date] => 2008-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9027 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20090070726.pdf [firstpage_image] =>[orig_patent_app_number] => 12062360 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/062360
Enhanced Routing Grid System and Method Apr 2, 2008 Abandoned
Array ( [id] => 4889164 [patent_doc_number] => 20080263496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Enhanced routing grid system and method' [patent_app_type] => utility [patent_app_number] => 12/062259 [patent_app_country] => US [patent_app_date] => 2008-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9028 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263496.pdf [firstpage_image] =>[orig_patent_app_number] => 12062259 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/062259
Enhanced routing grid system and method Apr 2, 2008 Abandoned
Array ( [id] => 4889166 [patent_doc_number] => 20080263498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Enhanced Routing Grid System and Method' [patent_app_type] => utility [patent_app_number] => 12/062308 [patent_app_country] => US [patent_app_date] => 2008-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9026 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263498.pdf [firstpage_image] =>[orig_patent_app_number] => 12062308 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/062308
Enhanced Routing Grid System and Method Apr 2, 2008 Abandoned
Array ( [id] => 4847779 [patent_doc_number] => 20080184187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Enhanced Routing Grid System and Method' [patent_app_type] => utility [patent_app_number] => 12/062363 [patent_app_country] => US [patent_app_date] => 2008-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9028 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20080184187.pdf [firstpage_image] =>[orig_patent_app_number] => 12062363 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/062363
Enhanced Routing Grid System and Method Apr 2, 2008 Abandoned
Array ( [id] => 4889165 [patent_doc_number] => 20080263497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-23 [patent_title] => 'Enhanced Routing Grid System and Method' [patent_app_type] => utility [patent_app_number] => 12/062286 [patent_app_country] => US [patent_app_date] => 2008-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9026 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20080263497.pdf [firstpage_image] =>[orig_patent_app_number] => 12062286 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/062286
Enhanced Routing Grid System and Method Apr 2, 2008 Abandoned
Array ( [id] => 600165 [patent_doc_number] => 07441216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-21 [patent_title] => 'Applying CNF simplification techniques for SAT-based abstraction refinement' [patent_app_type] => utility [patent_app_number] => 12/060260 [patent_app_country] => US [patent_app_date] => 2008-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2143 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/441/07441216.pdf [firstpage_image] =>[orig_patent_app_number] => 12060260 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/060260
Applying CNF simplification techniques for SAT-based abstraction refinement Mar 30, 2008 Issued
Array ( [id] => 4528423 [patent_doc_number] => 07934185 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-04-26 [patent_title] => 'Method of simulating bidirectional signals in a modeling system' [patent_app_type] => utility [patent_app_number] => 12/054247 [patent_app_country] => US [patent_app_date] => 2008-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/934/07934185.pdf [firstpage_image] =>[orig_patent_app_number] => 12054247 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/054247
Method of simulating bidirectional signals in a modeling system Mar 23, 2008 Issued
Array ( [id] => 5351689 [patent_doc_number] => 20090007050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'System for designing re-programmable digital hardware platforms' [patent_app_type] => utility [patent_app_number] => 12/074674 [patent_app_country] => US [patent_app_date] => 2008-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20090007050.pdf [firstpage_image] =>[orig_patent_app_number] => 12074674 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/074674
System for designing re-programmable digital hardware platforms Mar 3, 2008 Abandoned
Array ( [id] => 4726226 [patent_doc_number] => 20080205767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'Extraction method, extraction apparatus, program, drawing data creation method, and drawing data creation apparatus' [patent_app_type] => utility [patent_app_number] => 12/068960 [patent_app_country] => US [patent_app_date] => 2008-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 17677 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0205/20080205767.pdf [firstpage_image] =>[orig_patent_app_number] => 12068960 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/068960
Extraction method, extraction apparatus, program, drawing data creation method, and drawing data creation apparatus Feb 12, 2008 Abandoned
Array ( [id] => 8001357 [patent_doc_number] => 08082526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Dedicated crossbar and barrel shifter block on programmable logic resources' [patent_app_type] => utility [patent_app_number] => 12/069830 [patent_app_country] => US [patent_app_date] => 2008-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 7970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/082/08082526.pdf [firstpage_image] =>[orig_patent_app_number] => 12069830 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/069830
Dedicated crossbar and barrel shifter block on programmable logic resources Feb 11, 2008 Issued
Array ( [id] => 4700404 [patent_doc_number] => 20080222588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Method and program for designing semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/068660 [patent_app_country] => US [patent_app_date] => 2008-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4371 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20080222588.pdf [firstpage_image] =>[orig_patent_app_number] => 12068660 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/068660
Method and program for designing semiconductor device Feb 7, 2008 Issued
Array ( [id] => 8461003 [patent_doc_number] => 08296690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-23 [patent_title] => 'Method and arrangement providing for implementation granularity using implementation sets' [patent_app_type] => utility [patent_app_number] => 12/027501 [patent_app_country] => US [patent_app_date] => 2008-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5362 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12027501 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/027501
Method and arrangement providing for implementation granularity using implementation sets Feb 6, 2008 Issued
Array ( [id] => 4523231 [patent_doc_number] => 07917878 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-03-29 [patent_title] => 'Method for place and route of multicore chip' [patent_app_type] => utility [patent_app_number] => 12/022950 [patent_app_country] => US [patent_app_date] => 2008-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/917/07917878.pdf [firstpage_image] =>[orig_patent_app_number] => 12022950 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/022950
Method for place and route of multicore chip Jan 29, 2008 Issued
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