Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4678396 [patent_doc_number] => 20080216027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Electronic Design for Integrated Circuits Based on Process Related Variations' [patent_app_type] => utility [patent_app_number] => 12/021298 [patent_app_country] => US [patent_app_date] => 2008-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 78 [patent_figures_cnt] => 78 [patent_no_of_words] => 25623 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216027.pdf [firstpage_image] =>[orig_patent_app_number] => 12021298 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/021298
Electronic design for integrated circuits based on process related variations Jan 27, 2008 Issued
Array ( [id] => 4449095 [patent_doc_number] => 07865847 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'Method and system for creating and programming an adaptive computing engine' [patent_app_type] => utility [patent_app_number] => 12/011340 [patent_app_country] => US [patent_app_date] => 2008-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4323 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/865/07865847.pdf [firstpage_image] =>[orig_patent_app_number] => 12011340 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/011340
Method and system for creating and programming an adaptive computing engine Jan 24, 2008 Issued
Array ( [id] => 4455163 [patent_doc_number] => 07966594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Automated method for the hierarchical and selective insertion of dummy surfaces into the physical design of a multilayer integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/007678 [patent_app_country] => US [patent_app_date] => 2008-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7933 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966594.pdf [firstpage_image] =>[orig_patent_app_number] => 12007678 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/007678
Automated method for the hierarchical and selective insertion of dummy surfaces into the physical design of a multilayer integrated circuit Jan 13, 2008 Issued
Array ( [id] => 4917742 [patent_doc_number] => 20080098343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-24 [patent_title] => 'System and method for text based placement engine for custom circuit design' [patent_app_type] => utility [patent_app_number] => 11/970787 [patent_app_country] => US [patent_app_date] => 2008-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4155 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20080098343.pdf [firstpage_image] =>[orig_patent_app_number] => 11970787 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/970787
System and method for text based placement engine for custom circuit design Jan 7, 2008 Issued
Array ( [id] => 4895459 [patent_doc_number] => 20080104559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Method and System for Enhanced Verification Through Structural Target Decomposition' [patent_app_type] => utility [patent_app_number] => 11/969761 [patent_app_country] => US [patent_app_date] => 2008-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8694 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104559.pdf [firstpage_image] =>[orig_patent_app_number] => 11969761 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969761
Method and System for Enhanced Verification Through Structural Target Decomposition Jan 3, 2008 Abandoned
Array ( [id] => 4895458 [patent_doc_number] => 20080104558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Method and System for Enhanced Verification Through Structural Target Decomposition' [patent_app_type] => utility [patent_app_number] => 11/969741 [patent_app_country] => US [patent_app_date] => 2008-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8692 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104558.pdf [firstpage_image] =>[orig_patent_app_number] => 11969741 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969741
Method and System for Enhanced Verification Through Structural Target Decomposition Jan 3, 2008 Abandoned
Array ( [id] => 4869167 [patent_doc_number] => 20080148201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Design Structure and System for Identification of Defects on Circuits or Other Arrayed Products' [patent_app_type] => utility [patent_app_number] => 11/969294 [patent_app_country] => US [patent_app_date] => 2008-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9057 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148201.pdf [firstpage_image] =>[orig_patent_app_number] => 11969294 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/969294
Design Structure and System for Identification of Defects on Circuits or Other Arrayed Products Jan 3, 2008 Abandoned
Array ( [id] => 5432093 [patent_doc_number] => 20090166679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'INTEGRATED CIRCUIT AND MANUFACTURING PROCESS FACILITATING SELECTIVE CONFIGURATION FOR ELECTROMAGNETIC COMPATIBILITY' [patent_app_type] => utility [patent_app_number] => 11/967880 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5980 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20090166679.pdf [firstpage_image] =>[orig_patent_app_number] => 11967880 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967880
Integrated circuit and manufacturing process facilitating selective configuration for electromagnetic compatibility Dec 30, 2007 Issued
Array ( [id] => 79757 [patent_doc_number] => 07752588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Timing driven force directed placement flow' [patent_app_type] => utility [patent_app_number] => 11/967180 [patent_app_country] => US [patent_app_date] => 2007-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 70 [patent_no_of_words] => 51533 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/752/07752588.pdf [firstpage_image] =>[orig_patent_app_number] => 11967180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967180
Timing driven force directed placement flow Dec 28, 2007 Issued
Array ( [id] => 4678394 [patent_doc_number] => 20080216025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Tunneling as a Boundary Congestion Relief Mechanism' [patent_app_type] => utility [patent_app_number] => 11/967185 [patent_app_country] => US [patent_app_date] => 2007-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 51514 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216025.pdf [firstpage_image] =>[orig_patent_app_number] => 11967185 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967185
Tunneling as a boundary congestion relief mechanism Dec 28, 2007 Issued
Array ( [id] => 4678408 [patent_doc_number] => 20080216039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Node Spreading via Artificial Density Enhancement to Reduce Routing Congestion' [patent_app_type] => utility [patent_app_number] => 11/967184 [patent_app_country] => US [patent_app_date] => 2007-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 51510 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20080216039.pdf [firstpage_image] =>[orig_patent_app_number] => 11967184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/967184
Node spreading via artificial density enhancement to reduce routing congestion Dec 28, 2007 Issued
Array ( [id] => 4479792 [patent_doc_number] => 07945881 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Method of reducing crosstalk induced noise in circuitry designs' [patent_app_type] => utility [patent_app_number] => 11/961440 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2700 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/945/07945881.pdf [firstpage_image] =>[orig_patent_app_number] => 11961440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/961440
Method of reducing crosstalk induced noise in circuitry designs Dec 19, 2007 Issued
Array ( [id] => 4869195 [patent_doc_number] => 20080148218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'MASK DATA GENERATION METHOD, MASK FORMATION METHOD, PATTERN FORMATION METHOD' [patent_app_type] => utility [patent_app_number] => 11/959610 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6149 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148218.pdf [firstpage_image] =>[orig_patent_app_number] => 11959610 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/959610
MASK DATA GENERATION METHOD, MASK FORMATION METHOD, PATTERN FORMATION METHOD Dec 18, 2007 Abandoned
Array ( [id] => 6619569 [patent_doc_number] => 20100050147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'METHOD AND DEVICE PROVIDING INTEGRATED CIRCUIT DESIGN ASSISTANCE' [patent_app_type] => utility [patent_app_number] => 12/519250 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7362 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20100050147.pdf [firstpage_image] =>[orig_patent_app_number] => 12519250 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/519250
METHOD AND DEVICE PROVIDING INTEGRATED CIRCUIT DESIGN ASSISTANCE Dec 12, 2007 Abandoned
Array ( [id] => 5424392 [patent_doc_number] => 20090150848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'Topologies and Methodologies for AMS Integrated Circuit Design' [patent_app_type] => utility [patent_app_number] => 11/927720 [patent_app_country] => US [patent_app_date] => 2007-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150848.pdf [firstpage_image] =>[orig_patent_app_number] => 11927720 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/927720
Topologies and methodologies for AMS integrated circuit design Dec 10, 2007 Issued
Array ( [id] => 5351677 [patent_doc_number] => 20090007038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'HYBRID COUNTEREXAMPLE GUIDED ABSTRACTION REFINEMENT' [patent_app_type] => utility [patent_app_number] => 11/950730 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9585 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20090007038.pdf [firstpage_image] =>[orig_patent_app_number] => 11950730 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/950730
HYBRID COUNTEREXAMPLE GUIDED ABSTRACTION REFINEMENT Dec 4, 2007 Abandoned
Array ( [id] => 4614392 [patent_doc_number] => 07996799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Verification technique' [patent_app_type] => utility [patent_app_number] => 11/923663 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4708 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/996/07996799.pdf [firstpage_image] =>[orig_patent_app_number] => 11923663 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923663
Verification technique Dec 2, 2007 Issued
Array ( [id] => 8716249 [patent_doc_number] => 08402402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-19 [patent_title] => 'Method for calculating a mixed I/O standard simultaneous switching noise (SSN) using a non-mixed I/O standard SSN model' [patent_app_type] => utility [patent_app_number] => 11/946380 [patent_app_country] => US [patent_app_date] => 2007-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5561 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11946380 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/946380
Method for calculating a mixed I/O standard simultaneous switching noise (SSN) using a non-mixed I/O standard SSN model Nov 27, 2007 Issued
Array ( [id] => 4462800 [patent_doc_number] => 07895556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes' [patent_app_type] => utility [patent_app_number] => 11/942990 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4677 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/895/07895556.pdf [firstpage_image] =>[orig_patent_app_number] => 11942990 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/942990
Method for optimizing an unrouted design to reduce the probability of timing problems due to coupling and long wire routes Nov 19, 2007 Issued
Array ( [id] => 4632004 [patent_doc_number] => 08010914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-30 [patent_title] => 'Circuit structure of integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/939560 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2494 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/010/08010914.pdf [firstpage_image] =>[orig_patent_app_number] => 11939560 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/939560
Circuit structure of integrated circuit Nov 13, 2007 Issued
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