Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4462788 [patent_doc_number] => 07895555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-22 [patent_title] => 'Simultaneous switching output noise estimation and reduction systems and methods' [patent_app_type] => utility [patent_app_number] => 11/937300 [patent_app_country] => US [patent_app_date] => 2007-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6311 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/895/07895555.pdf [firstpage_image] =>[orig_patent_app_number] => 11937300 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/937300
Simultaneous switching output noise estimation and reduction systems and methods Nov 7, 2007 Issued
Array ( [id] => 4874936 [patent_doc_number] => 20080201670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-21 [patent_title] => 'Using constrained scan cells to test integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/983533 [patent_app_country] => US [patent_app_date] => 2007-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13366 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20080201670.pdf [firstpage_image] =>[orig_patent_app_number] => 11983533 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/983533
Using constrained scan cells to test integrated circuits Nov 7, 2007 Abandoned
Array ( [id] => 4560448 [patent_doc_number] => 07877723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Method of arranging mask patterns and apparatus using the method' [patent_app_type] => utility [patent_app_number] => 11/936610 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4816 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/877/07877723.pdf [firstpage_image] =>[orig_patent_app_number] => 11936610 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/936610
Method of arranging mask patterns and apparatus using the method Nov 6, 2007 Issued
Array ( [id] => 4706520 [patent_doc_number] => 20080066044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Enhanced Routing Grid System And Method' [patent_app_type] => utility [patent_app_number] => 11/934554 [patent_app_country] => US [patent_app_date] => 2007-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9027 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20080066044.pdf [firstpage_image] =>[orig_patent_app_number] => 11934554 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934554
Enhanced Routing Grid System And Method Nov 1, 2007 Abandoned
Array ( [id] => 4774273 [patent_doc_number] => 20080059935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Enhanced Routing Grid System And Method' [patent_app_type] => utility [patent_app_number] => 11/934543 [patent_app_country] => US [patent_app_date] => 2007-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9037 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059935.pdf [firstpage_image] =>[orig_patent_app_number] => 11934543 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934543
Enhanced Routing Grid System And Method Nov 1, 2007 Abandoned
Array ( [id] => 4923884 [patent_doc_number] => 20080072201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Enhanced Routing Grid System And Method' [patent_app_type] => utility [patent_app_number] => 11/934527 [patent_app_country] => US [patent_app_date] => 2007-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9026 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072201.pdf [firstpage_image] =>[orig_patent_app_number] => 11934527 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934527
Enhanced Routing Grid System And Method Nov 1, 2007 Abandoned
Array ( [id] => 4774274 [patent_doc_number] => 20080059936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'Enhanced Routing Grid System And Method' [patent_app_type] => utility [patent_app_number] => 11/934565 [patent_app_country] => US [patent_app_date] => 2007-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9033 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20080059936.pdf [firstpage_image] =>[orig_patent_app_number] => 11934565 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/934565
Enhanced Routing Grid System And Method Nov 1, 2007 Abandoned
Array ( [id] => 5328423 [patent_doc_number] => 20090108900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'APPARATUS AND METHOD FOR OPTIMIZING DELAY ELEMENT IN ASYNCHRONOUS DIGITAL CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/933230 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4636 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20090108900.pdf [firstpage_image] =>[orig_patent_app_number] => 11933230 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933230
Apparatus and method for optimizing delay element in asynchronous digital circuits Oct 30, 2007 Issued
Array ( [id] => 4895467 [patent_doc_number] => 20080104567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'APPARATUS AND METHOD FOR ALLOCATING COMPONENT, AND COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 11/924820 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6086 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104567.pdf [firstpage_image] =>[orig_patent_app_number] => 11924820 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/924820
APPARATUS AND METHOD FOR ALLOCATING COMPONENT, AND COMPUTER READABLE MEDIUM Oct 25, 2007 Abandoned
Array ( [id] => 4945456 [patent_doc_number] => 20080082783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-03 [patent_title] => 'Dual Independent and Shared Resource Vector Execution Units with Shared Register File' [patent_app_type] => utility [patent_app_number] => 11/924980 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9652 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20080082783.pdf [firstpage_image] =>[orig_patent_app_number] => 11924980 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/924980
Dual independent and shared resource vector execution units with shared register file Oct 25, 2007 Issued
Array ( [id] => 4487497 [patent_doc_number] => 07870516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same' [patent_app_type] => utility [patent_app_number] => 11/976522 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 6369 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/870/07870516.pdf [firstpage_image] =>[orig_patent_app_number] => 11976522 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/976522
Asynchronous, multi-rail, asymmetric-phase, static digital logic with completion detection and method for designing the same Oct 24, 2007 Issued
Array ( [id] => 4775988 [patent_doc_number] => 20080283986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-20 [patent_title] => 'System-in-package type semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/977463 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13776 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20080283986.pdf [firstpage_image] =>[orig_patent_app_number] => 11977463 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/977463
System-in-package type semiconductor device Oct 24, 2007 Abandoned
Array ( [id] => 69227 [patent_doc_number] => 07761839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Performance in model-based OPC engine utilizing efficient polygon pinning method' [patent_app_type] => utility [patent_app_number] => 11/874274 [patent_app_country] => US [patent_app_date] => 2007-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761839.pdf [firstpage_image] =>[orig_patent_app_number] => 11874274 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/874274
Performance in model-based OPC engine utilizing efficient polygon pinning method Oct 17, 2007 Issued
Array ( [id] => 4747544 [patent_doc_number] => 20080092146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'COMPUTING MACHINE' [patent_app_type] => utility [patent_app_number] => 11/869270 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5783 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20080092146.pdf [firstpage_image] =>[orig_patent_app_number] => 11869270 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/869270
COMPUTING MACHINE Oct 8, 2007 Abandoned
Array ( [id] => 8667669 [patent_doc_number] => 08381142 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-19 [patent_title] => 'Using a timing exception to postpone retiming' [patent_app_type] => utility [patent_app_number] => 11/973470 [patent_app_country] => US [patent_app_date] => 2007-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7715 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11973470 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/973470
Using a timing exception to postpone retiming Oct 8, 2007 Issued
Array ( [id] => 4755065 [patent_doc_number] => 20080163141 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'SUPPLANT DESIGN RULES IN ELECTRONIC DESIGNS' [patent_app_type] => utility [patent_app_number] => 11/866370 [patent_app_country] => US [patent_app_date] => 2007-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8280 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20080163141.pdf [firstpage_image] =>[orig_patent_app_number] => 11866370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/866370
Supplant design rules in electronic designs Oct 1, 2007 Issued
Array ( [id] => 97120 [patent_doc_number] => 07735028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Logic circuit redesign program, logic circuit redesign apparatus, and logic circuit redesign method' [patent_app_type] => utility [patent_app_number] => 11/902050 [patent_app_country] => US [patent_app_date] => 2007-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 8261 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/735/07735028.pdf [firstpage_image] =>[orig_patent_app_number] => 11902050 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/902050
Logic circuit redesign program, logic circuit redesign apparatus, and logic circuit redesign method Sep 17, 2007 Issued
Array ( [id] => 8401516 [patent_doc_number] => 08271911 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-09-18 [patent_title] => 'Programmable hardware event reporting' [patent_app_type] => utility [patent_app_number] => 11/901100 [patent_app_country] => US [patent_app_date] => 2007-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11901100 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/901100
Programmable hardware event reporting Sep 12, 2007 Issued
Array ( [id] => 4741999 [patent_doc_number] => 20080235652 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'Lithography method for forming a circuit pattern' [patent_app_type] => utility [patent_app_number] => 11/897600 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4510 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20080235652.pdf [firstpage_image] =>[orig_patent_app_number] => 11897600 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/897600
Lithography method for forming a circuit pattern Aug 30, 2007 Issued
Array ( [id] => 4706516 [patent_doc_number] => 20080066040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Integrated Circuit Chip With Repeater Flops and Method for Automated Design of Same' [patent_app_type] => utility [patent_app_number] => 11/840660 [patent_app_country] => US [patent_app_date] => 2007-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6731 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20080066040.pdf [firstpage_image] =>[orig_patent_app_number] => 11840660 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/840660
Integrated Circuit Chip With Repeater Flops and Method for Automated Design of Same Aug 16, 2007 Abandoned
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