Paul Dinh

Array ( [id] => 4669873 [patent_doc_number] => 20080044933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'Method for forming matching table of inner pads and outer pads and method for matching inner pads with outer pads using the same' [patent_app_type] => utility [patent_app_number] => 11/889790 [patent_app_country] => US [patent_app_date] => 2007-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20080044933.pdf [firstpage_image] =>[orig_patent_app_number] => 11889790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7972387 [patent_doc_number] => 07941772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Dynamic critical path detector for digital logic circuit paths' [patent_app_type] => utility [patent_app_number] => 11/834110 [patent_app_country] => US [patent_app_date] => 2007-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4380 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/941/07941772.pdf [firstpage_image] =>[orig_patent_app_number] => 11834110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4911466 [patent_doc_number] => 20080022233 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-24 [patent_title] => 'Method, Apparatus, and Computer Program Product for Enhancing a Power Distribution System in a Ceramic Integrated Circuit Package' [patent_app_type] => utility [patent_app_number] => 11/832453 [patent_app_country] => US [patent_app_date] => 2007-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20080022233.pdf [firstpage_image] =>[orig_patent_app_number] => 11832453 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4655312 [patent_doc_number] => 20080024173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'Semiconductor integrated circuit including a malfunction detection circuit, and a design method for the same' [patent_app_type] => utility [patent_app_number] => 11/878520 [patent_app_country] => US [patent_app_date] => 2007-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 12151 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20080024173.pdf [firstpage_image] =>[orig_patent_app_number] => 11878520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9105 [patent_doc_number] => 07818696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores' [patent_app_type] => utility [patent_app_number] => 11/780712 [patent_app_country] => US [patent_app_date] => 2007-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4601 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818696.pdf [firstpage_image] =>[orig_patent_app_number] => 11780712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4659480 [patent_doc_number] => 20080028342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-31 [patent_title] => 'SIMULATION APPARATUS AND SIMULATION METHOD USED TO DESIGN CHARACTERISTICS AND CIRCUITS OF SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 11/776730 [patent_app_country] => US [patent_app_date] => 2007-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12492 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20080028342.pdf [firstpage_image] =>[orig_patent_app_number] => 11776730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5298366 [patent_doc_number] => 20090013292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-08 [patent_title] => 'CONTEXT DEPENDENT TIMING ANALYSIS AND PREDICTION' [patent_app_type] => utility [patent_app_number] => 11/773390 [patent_app_country] => US [patent_app_date] => 2007-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6246 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20090013292.pdf [firstpage_image] =>[orig_patent_app_number] => 11773390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5351671 [patent_doc_number] => 20090007032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'METHOD AND APPARATUS FOR SUBSTRATE NOISE ANALYSIS USING SUBSTRATE TILE MODEL AND TILE GRID' [patent_app_type] => utility [patent_app_number] => 11/769670 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20090007032.pdf [firstpage_image] =>[orig_patent_app_number] => 11769670 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5351666 [patent_doc_number] => 20090007027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'TRANSLATING A USER DESIGN IN A CONFIGURABLE IC FOR DEBUGGING THE USER DESIGN' [patent_app_type] => utility [patent_app_number] => 11/769680 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 24881 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20090007027.pdf [firstpage_image] =>[orig_patent_app_number] => 11769680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4590193 [patent_doc_number] => 07861203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Method and system for model-based routing of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/768839 [patent_app_country] => US [patent_app_date] => 2007-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8009 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/861/07861203.pdf [firstpage_image] =>[orig_patent_app_number] => 11768839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4500822 [patent_doc_number] => 07904861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Method, system, and computer program product for coupled noise timing violation avoidance in detailed routing' [patent_app_type] => utility [patent_app_number] => 11/762130 [patent_app_country] => US [patent_app_date] => 2007-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 9101 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/904/07904861.pdf [firstpage_image] =>[orig_patent_app_number] => 11762130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4951255 [patent_doc_number] => 20080307381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-11 [patent_title] => 'IC LAYOUT PARSING FOR MULTIPLE MASKS' [patent_app_type] => utility [patent_app_number] => 11/758510 [patent_app_country] => US [patent_app_date] => 2007-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6704 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20080307381.pdf [firstpage_image] =>[orig_patent_app_number] => 11758510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4804887 [patent_doc_number] => 20080016476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'HIERARCHICAL ANALOG LAYOUT SYNTHESIS AND OPTIMIZATION FOR INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/757350 [patent_app_country] => US [patent_app_date] => 2007-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8149 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016476.pdf [firstpage_image] =>[orig_patent_app_number] => 11757350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5065035 [patent_doc_number] => 20070226677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'PERFORMANCE IN MODEL-BASED OPC ENGINE UTILIZING EFFICIENT POLYGON PINNING METHOD' [patent_app_type] => utility [patent_app_number] => 11/756883 [patent_app_country] => US [patent_app_date] => 2007-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7555 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226677.pdf [firstpage_image] =>[orig_patent_app_number] => 11756883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4838216 [patent_doc_number] => 20080278701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-13 [patent_title] => 'DEFOCUS DETERMINATION METHOD USING SUB-RESOLUTION FEATURE (SRF) PRINTING' [patent_app_type] => utility [patent_app_number] => 11/746970 [patent_app_country] => US [patent_app_date] => 2007-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4309 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20080278701.pdf [firstpage_image] =>[orig_patent_app_number] => 11746970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5257195 [patent_doc_number] => 20070210827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Application-specific integrated circuit equivalents of programmable logic and associated methods' [patent_app_type] => utility [patent_app_number] => 11/801082 [patent_app_country] => US [patent_app_date] => 2007-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8390 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210827.pdf [firstpage_image] =>[orig_patent_app_number] => 11801082 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5212219 [patent_doc_number] => 20070250803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'High-level synthesis method and high-level synthesis system' [patent_app_type] => utility [patent_app_number] => 11/785800 [patent_app_country] => US [patent_app_date] => 2007-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7728 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20070250803.pdf [firstpage_image] =>[orig_patent_app_number] => 11785800 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4693940 [patent_doc_number] => 20080086711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'Method and apparatus for designing integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/785430 [patent_app_country] => US [patent_app_date] => 2007-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10724 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20080086711.pdf [firstpage_image] =>[orig_patent_app_number] => 11785430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4447679 [patent_doc_number] => 07930653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Triangulating design data and encoding design intent for microlithographic printing' [patent_app_type] => utility [patent_app_number] => 11/736490 [patent_app_country] => US [patent_app_date] => 2007-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 9309 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930653.pdf [firstpage_image] =>[orig_patent_app_number] => 11736490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4590518 [patent_doc_number] => 07831943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-09 [patent_title] => 'Checking for valid slice packing in a programmable device' [patent_app_type] => utility [patent_app_number] => 11/787600 [patent_app_country] => US [patent_app_date] => 2007-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4301 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831943.pdf [firstpage_image] =>[orig_patent_app_number] => 11787600 [rel_patent_id] =>[rel_patent_doc_number] =>)