Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 69217 [patent_doc_number] => 07761830 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-07-20 [patent_title] => 'Method and system for providing placement based configurations in integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/786192 [patent_app_country] => US [patent_app_date] => 2007-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3088 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761830.pdf [firstpage_image] =>[orig_patent_app_number] => 11786192 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/786192
Method and system for providing placement based configurations in integrated circuits Apr 9, 2007 Issued
Array ( [id] => 4684143 [patent_doc_number] => 20080250369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Method of estimating the signal delay in a VLSI circuit' [patent_app_type] => utility [patent_app_number] => 11/733030 [patent_app_country] => US [patent_app_date] => 2007-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3092 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250369.pdf [firstpage_image] =>[orig_patent_app_number] => 11733030 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/733030
Method of estimating the signal delay in a VLSI circuit Apr 8, 2007 Issued
Array ( [id] => 166930 [patent_doc_number] => 07673264 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-02 [patent_title] => 'System and method for verifying IP integrity in system-on-chip (SOC) design' [patent_app_type] => utility [patent_app_number] => 11/732900 [patent_app_country] => US [patent_app_date] => 2007-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3826 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/673/07673264.pdf [firstpage_image] =>[orig_patent_app_number] => 11732900 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/732900
System and method for verifying IP integrity in system-on-chip (SOC) design Apr 4, 2007 Issued
Array ( [id] => 7542997 [patent_doc_number] => 08060846 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-15 [patent_title] => 'Inductance mitigation through switching density analysis' [patent_app_type] => utility [patent_app_number] => 11/732950 [patent_app_country] => US [patent_app_date] => 2007-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3865 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/060/08060846.pdf [firstpage_image] =>[orig_patent_app_number] => 11732950 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/732950
Inductance mitigation through switching density analysis Apr 3, 2007 Issued
Array ( [id] => 4447678 [patent_doc_number] => 07930652 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Timing circuit CAD' [patent_app_type] => utility [patent_app_number] => 11/694839 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 35 [patent_no_of_words] => 13262 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/930/07930652.pdf [firstpage_image] =>[orig_patent_app_number] => 11694839 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694839
Timing circuit CAD Mar 29, 2007 Issued
Array ( [id] => 5065029 [patent_doc_number] => 20070226671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Apparatus and method of static timing analysis considering the within-die and die-to-die process variation' [patent_app_type] => utility [patent_app_number] => 11/723580 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10340 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20070226671.pdf [firstpage_image] =>[orig_patent_app_number] => 11723580 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/723580
Apparatus and method of static timing analysis considering the within-die and die-to-die process variation Mar 20, 2007 Abandoned
Array ( [id] => 156364 [patent_doc_number] => 07681167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'System and apparatus for designing layout of a LSI' [patent_app_type] => utility [patent_app_number] => 11/723320 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 11653 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/681/07681167.pdf [firstpage_image] =>[orig_patent_app_number] => 11723320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/723320
System and apparatus for designing layout of a LSI Mar 18, 2007 Issued
Array ( [id] => 4626893 [patent_doc_number] => 08006205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Semiconductor device layout method, a computer program, and a semiconductor device manufacture method' [patent_app_type] => utility [patent_app_number] => 11/715246 [patent_app_country] => US [patent_app_date] => 2007-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 2792 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/006/08006205.pdf [firstpage_image] =>[orig_patent_app_number] => 11715246 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/715246
Semiconductor device layout method, a computer program, and a semiconductor device manufacture method Mar 5, 2007 Issued
Array ( [id] => 325430 [patent_doc_number] => 07519939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-14 [patent_title] => 'Method and program for supporting register-transfer-level design of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/680090 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 26 [patent_no_of_words] => 7902 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/519/07519939.pdf [firstpage_image] =>[orig_patent_app_number] => 11680090 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/680090
Method and program for supporting register-transfer-level design of semiconductor integrated circuit Feb 27, 2007 Issued
Array ( [id] => 5516909 [patent_doc_number] => 20090217216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'CARBON NANOTUBE CIRCUITS DESIGN METHODOLOGY' [patent_app_type] => utility [patent_app_number] => 11/680350 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3374 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20090217216.pdf [firstpage_image] =>[orig_patent_app_number] => 11680350 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/680350
CARBON NANOTUBE CIRCUITS DESIGN METHODOLOGY Feb 27, 2007 Abandoned
Array ( [id] => 28582 [patent_doc_number] => 07797657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Parameter ordering for multi-corner static timing analysis' [patent_app_type] => utility [patent_app_number] => 11/679831 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9223 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/797/07797657.pdf [firstpage_image] =>[orig_patent_app_number] => 11679831 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679831
Parameter ordering for multi-corner static timing analysis Feb 26, 2007 Issued
Array ( [id] => 19181 [patent_doc_number] => 07810056 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-05 [patent_title] => 'Method and system for implementing context aware synthesis of assertions' [patent_app_type] => utility [patent_app_number] => 11/711950 [patent_app_country] => US [patent_app_date] => 2007-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5641 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/810/07810056.pdf [firstpage_image] =>[orig_patent_app_number] => 11711950 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/711950
Method and system for implementing context aware synthesis of assertions Feb 26, 2007 Issued
Array ( [id] => 47957 [patent_doc_number] => 07784003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Estimation of process variation impact of slack in multi-corner path-based static timing analysis' [patent_app_type] => utility [patent_app_number] => 11/679171 [patent_app_country] => US [patent_app_date] => 2007-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/784/07784003.pdf [firstpage_image] =>[orig_patent_app_number] => 11679171 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/679171
Estimation of process variation impact of slack in multi-corner path-based static timing analysis Feb 25, 2007 Issued
Array ( [id] => 9109 [patent_doc_number] => 07818699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-19 [patent_title] => 'Dynamic core pipeline' [patent_app_type] => utility [patent_app_number] => 11/706440 [patent_app_country] => US [patent_app_date] => 2007-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5277 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818699.pdf [firstpage_image] =>[orig_patent_app_number] => 11706440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/706440
Dynamic core pipeline Feb 13, 2007 Issued
Array ( [id] => 7525088 [patent_doc_number] => 08028258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-09-27 [patent_title] => 'Interactive graphical pin assignment' [patent_app_type] => utility [patent_app_number] => 11/707200 [patent_app_country] => US [patent_app_date] => 2007-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6852 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/028/08028258.pdf [firstpage_image] =>[orig_patent_app_number] => 11707200 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/707200
Interactive graphical pin assignment Feb 13, 2007 Issued
Array ( [id] => 137344 [patent_doc_number] => 07698663 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Apparatus, method and program for designing integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/703700 [patent_app_country] => US [patent_app_date] => 2007-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6996 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698663.pdf [firstpage_image] =>[orig_patent_app_number] => 11703700 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703700
Apparatus, method and program for designing integrated circuit Feb 7, 2007 Issued
Array ( [id] => 5260814 [patent_doc_number] => 20070214447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'Behavioral synthesis apparatus, behavioral synthesis method, method for manufacturing digital circuit, behavioral synthesis control program and computer-readable recording medium' [patent_app_type] => utility [patent_app_number] => 11/703140 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9595 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20070214447.pdf [firstpage_image] =>[orig_patent_app_number] => 11703140 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/703140
Behavioral synthesis apparatus, behavioral synthesis method, method for manufacturing digital circuit, behavioral synthesis control program and computer-readable recording medium Feb 6, 2007 Issued
Array ( [id] => 4956070 [patent_doc_number] => 20080189094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'Systematic Compliance Checking of a Process' [patent_app_type] => utility [patent_app_number] => 11/672050 [patent_app_country] => US [patent_app_date] => 2007-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20080189094.pdf [firstpage_image] =>[orig_patent_app_number] => 11672050 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/672050
Systematic compliance checking of a process Feb 6, 2007 Issued
Array ( [id] => 5097217 [patent_doc_number] => 20070118826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'OPC CONFLICT IDENTIFICATION AND EDGE PRIORITY SYSTEM' [patent_app_type] => utility [patent_app_number] => 11/626307 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3147 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20070118826.pdf [firstpage_image] =>[orig_patent_app_number] => 11626307 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/626307
OPC conflict identification and edge priority system Jan 22, 2007 Issued
Array ( [id] => 156350 [patent_doc_number] => 07681153 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Estimating static power consumption of integrated circuits using logic gate templates' [patent_app_type] => utility [patent_app_number] => 11/626020 [patent_app_country] => US [patent_app_date] => 2007-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5839 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/681/07681153.pdf [firstpage_image] =>[orig_patent_app_number] => 11626020 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/626020
Estimating static power consumption of integrated circuits using logic gate templates Jan 22, 2007 Issued
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