Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5161756 [patent_doc_number] => 20070174800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Methods and systems for analyzing layouts of semiconductor integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 11/654340 [patent_app_country] => US [patent_app_date] => 2007-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7555 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20070174800.pdf [firstpage_image] =>[orig_patent_app_number] => 11654340 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/654340
Methods and systems for analyzing layouts of semiconductor integrated circuit devices Jan 16, 2007 Issued
Array ( [id] => 188767 [patent_doc_number] => 07647566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Method for creating new via' [patent_app_type] => utility [patent_app_number] => 11/649220 [patent_app_country] => US [patent_app_date] => 2007-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2696 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/647/07647566.pdf [firstpage_image] =>[orig_patent_app_number] => 11649220 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/649220
Method for creating new via Jan 3, 2007 Issued
Array ( [id] => 272393 [patent_doc_number] => 07565633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-21 [patent_title] => 'Verifying mask layout printability using simulation with adjustable accuracy' [patent_app_type] => utility [patent_app_number] => 11/619320 [patent_app_country] => US [patent_app_date] => 2007-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5802 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/565/07565633.pdf [firstpage_image] =>[orig_patent_app_number] => 11619320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/619320
Verifying mask layout printability using simulation with adjustable accuracy Jan 2, 2007 Issued
Array ( [id] => 137347 [patent_doc_number] => 07698666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Method and system for model-based design and layout of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/648150 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4112 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698666.pdf [firstpage_image] =>[orig_patent_app_number] => 11648150 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648150
Method and system for model-based design and layout of an integrated circuit Dec 28, 2006 Issued
Array ( [id] => 4882107 [patent_doc_number] => 20080155490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'Method for Reducing Coupling Noise, Reducing Signal Skew, and Saving Layout Area for an Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 11/615270 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5130 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20080155490.pdf [firstpage_image] =>[orig_patent_app_number] => 11615270 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/615270
Method for Reducing Coupling Noise, Reducing Signal Skew, and Saving Layout Area for an Integrated Circuit Dec 21, 2006 Abandoned
Array ( [id] => 4882099 [patent_doc_number] => 20080155482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'AUTOMATED OPTIMIZATION OF VLSI LAYOUTS FOR REGULARITY' [patent_app_type] => utility [patent_app_number] => 11/614260 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2652 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20080155482.pdf [firstpage_image] =>[orig_patent_app_number] => 11614260 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/614260
AUTOMATED OPTIMIZATION OF VLSI LAYOUTS FOR REGULARITY Dec 20, 2006 Abandoned
Array ( [id] => 4869014 [patent_doc_number] => 20080148073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Method for providing secure and trusted ASICs using 3D integration' [patent_app_type] => utility [patent_app_number] => 11/638530 [patent_app_country] => US [patent_app_date] => 2006-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3042 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20080148073.pdf [firstpage_image] =>[orig_patent_app_number] => 11638530 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/638530
Method for providing secure and trusted ASICs using 3D integration Dec 13, 2006 Issued
Array ( [id] => 4984522 [patent_doc_number] => 20070089081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-19 [patent_title] => 'Net/wiring selection method, net selection method, wiring selection method, and delay improvement method' [patent_app_type] => utility [patent_app_number] => 11/637728 [patent_app_country] => US [patent_app_date] => 2006-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10047 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20070089081.pdf [firstpage_image] =>[orig_patent_app_number] => 11637728 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/637728
Net/wiring selection method, net selection method, wiring selection method, and delay improvement method Dec 12, 2006 Issued
Array ( [id] => 188793 [patent_doc_number] => 07647575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Method of creating a netlist for an FPGA and an ASIC' [patent_app_type] => utility [patent_app_number] => 11/636606 [patent_app_country] => US [patent_app_date] => 2006-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 38 [patent_no_of_words] => 22975 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/647/07647575.pdf [firstpage_image] =>[orig_patent_app_number] => 11636606 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/636606
Method of creating a netlist for an FPGA and an ASIC Dec 10, 2006 Issued
Array ( [id] => 4787871 [patent_doc_number] => 20080141200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Methods and apparatuses for timing analysis of electronic circuits' [patent_app_type] => utility [patent_app_number] => 11/635380 [patent_app_country] => US [patent_app_date] => 2006-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7428 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20080141200.pdf [firstpage_image] =>[orig_patent_app_number] => 11635380 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/635380
Methods and apparatuses for timing analysis of electronic circuits Dec 6, 2006 Issued
Array ( [id] => 5238402 [patent_doc_number] => 20070130559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'Optical Proximity Correction on Hardware or Software Platforms with Graphical Processing Units' [patent_app_type] => utility [patent_app_number] => 11/566140 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7551 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20070130559.pdf [firstpage_image] =>[orig_patent_app_number] => 11566140 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/566140
Optical proximity correction on hardware or software platforms with graphical processing units Nov 30, 2006 Issued
Array ( [id] => 146892 [patent_doc_number] => 07689967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Reference image generation from subject image for photolithography mask analysis' [patent_app_type] => utility [patent_app_number] => 11/556673 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7134 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689967.pdf [firstpage_image] =>[orig_patent_app_number] => 11556673 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/556673
Reference image generation from subject image for photolithography mask analysis Nov 2, 2006 Issued
Array ( [id] => 4830534 [patent_doc_number] => 20080127022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'Method for managing net data of a layout' [patent_app_type] => utility [patent_app_number] => 11/592120 [patent_app_country] => US [patent_app_date] => 2006-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1295 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20080127022.pdf [firstpage_image] =>[orig_patent_app_number] => 11592120 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/592120
Method for managing net data of a layout Nov 2, 2006 Abandoned
Array ( [id] => 4966953 [patent_doc_number] => 20080109773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-08 [patent_title] => 'Analyzing Impedance Discontinuities In A Printed Circuit Board' [patent_app_type] => utility [patent_app_number] => 11/555750 [patent_app_country] => US [patent_app_date] => 2006-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7038 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20080109773.pdf [firstpage_image] =>[orig_patent_app_number] => 11555750 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/555750
Analyzing Impedance Discontinuities In A Printed Circuit Board Nov 1, 2006 Abandoned
Array ( [id] => 5036764 [patent_doc_number] => 20070101303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Method and apparatus for integrated circuit layout optimization' [patent_app_type] => utility [patent_app_number] => 11/590840 [patent_app_country] => US [patent_app_date] => 2006-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5861 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20070101303.pdf [firstpage_image] =>[orig_patent_app_number] => 11590840 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/590840
Method and apparatus for integrated circuit layout optimization Oct 31, 2006 Abandoned
Array ( [id] => 4934933 [patent_doc_number] => 20080005708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Verification apparatus, design verification method, and computer aided design apparatus' [patent_app_type] => utility [patent_app_number] => 11/589170 [patent_app_country] => US [patent_app_date] => 2006-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9142 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20080005708.pdf [firstpage_image] =>[orig_patent_app_number] => 11589170 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/589170
Verification apparatus, design verification method, and computer aided design apparatus Oct 29, 2006 Issued
Array ( [id] => 118456 [patent_doc_number] => 07716609 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-05-11 [patent_title] => 'Method of circuit optimization utilizing programmable sleep transistors' [patent_app_type] => utility [patent_app_number] => 11/588380 [patent_app_country] => US [patent_app_date] => 2006-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4331 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/716/07716609.pdf [firstpage_image] =>[orig_patent_app_number] => 11588380 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/588380
Method of circuit optimization utilizing programmable sleep transistors Oct 25, 2006 Issued
Array ( [id] => 5102946 [patent_doc_number] => 20070186208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Mask-Pattern Determination Using Topology Types' [patent_app_type] => utility [patent_app_number] => 11/538420 [patent_app_country] => US [patent_app_date] => 2006-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4641 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20070186208.pdf [firstpage_image] =>[orig_patent_app_number] => 11538420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538420
Mask-pattern determination using topology types Oct 2, 2006 Issued
Array ( [id] => 4895450 [patent_doc_number] => 20080104550 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'COMPENSATING FOR LAYOUT DIMENSION EFFECTS IN SEMICONDUCTOR DEVICE MODELING' [patent_app_type] => utility [patent_app_number] => 11/537390 [patent_app_country] => US [patent_app_date] => 2006-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3555 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20080104550.pdf [firstpage_image] =>[orig_patent_app_number] => 11537390 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/537390
Compensating for layout dimension effects in semiconductor device modeling Sep 28, 2006 Issued
Array ( [id] => 198603 [patent_doc_number] => 07636905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-22 [patent_title] => 'Performing static timing analysis of an integrated circuit design using dummy edge modeling' [patent_app_type] => utility [patent_app_number] => 11/535510 [patent_app_country] => US [patent_app_date] => 2006-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5262 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/636/07636905.pdf [firstpage_image] =>[orig_patent_app_number] => 11535510 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/535510
Performing static timing analysis of an integrated circuit design using dummy edge modeling Sep 26, 2006 Issued
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