
Paul Dinh
Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2816, 2825 |
| Total Applications | 2030 |
| Issued Applications | 1783 |
| Pending Applications | 89 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[id] => 5161756
[patent_doc_number] => 20070174800
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[patent_title] => 'Methods and systems for analyzing layouts of semiconductor integrated circuit devices'
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Array
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Array
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Array
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Array
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Array
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[patent_title] => 'Method for providing secure and trusted ASICs using 3D integration'
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Array
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[patent_title] => 'Net/wiring selection method, net selection method, wiring selection method, and delay improvement method'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/636606 | Method of creating a netlist for an FPGA and an ASIC | Dec 10, 2006 | Issued |
Array
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Array
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Array
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Array
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Array
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Array
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