Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5171883 [patent_doc_number] => 20070072316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Wiring pattern determination method and computer program product thereof' [patent_app_type] => utility [patent_app_number] => 11/527250 [patent_app_country] => US [patent_app_date] => 2006-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7456 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072316.pdf [firstpage_image] =>[orig_patent_app_number] => 11527250 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/527250
Wiring pattern determination method and computer program product thereof Sep 24, 2006 Issued
Array ( [id] => 7689771 [patent_doc_number] => 20070234262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Method and apparatus for inspecting element layout in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/523040 [patent_app_country] => US [patent_app_date] => 2006-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7904 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234262.pdf [firstpage_image] =>[orig_patent_app_number] => 11523040 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/523040
Method and apparatus for inspecting element layout in semiconductor device Sep 18, 2006 Abandoned
Array ( [id] => 5107147 [patent_doc_number] => 20070066025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-22 [patent_title] => 'Pattern forming method, computer program thereof, and semiconductor device manufacturing method using the computer program' [patent_app_type] => utility [patent_app_number] => 11/521440 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20070066025.pdf [firstpage_image] =>[orig_patent_app_number] => 11521440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/521440
Pattern forming method, computer program thereof, and semiconductor device manufacturing method using the computer program Sep 14, 2006 Issued
Array ( [id] => 198604 [patent_doc_number] => 07636906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-22 [patent_title] => 'Semiconductor integrated circuit and layout designing method of the same' [patent_app_type] => utility [patent_app_number] => 11/521490 [patent_app_country] => US [patent_app_date] => 2006-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 6641 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/636/07636906.pdf [firstpage_image] =>[orig_patent_app_number] => 11521490 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/521490
Semiconductor integrated circuit and layout designing method of the same Sep 14, 2006 Issued
Array ( [id] => 302233 [patent_doc_number] => 07539952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/522049 [patent_app_country] => US [patent_app_date] => 2006-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 99 [patent_no_of_words] => 22515 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539952.pdf [firstpage_image] =>[orig_patent_app_number] => 11522049 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/522049
Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit Sep 13, 2006 Issued
Array ( [id] => 5190585 [patent_doc_number] => 20070168894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Method and device for supporting verification, and computer product' [patent_app_type] => utility [patent_app_number] => 11/520940 [patent_app_country] => US [patent_app_date] => 2006-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11040 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20070168894.pdf [firstpage_image] =>[orig_patent_app_number] => 11520940 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/520940
Method and device for supporting verification, and computer product Sep 13, 2006 Issued
Array ( [id] => 241481 [patent_doc_number] => 07594207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-22 [patent_title] => 'Computationally efficient design rule checking for circuit interconnect routing design' [patent_app_type] => utility [patent_app_number] => 11/521270 [patent_app_country] => US [patent_app_date] => 2006-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5550 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/594/07594207.pdf [firstpage_image] =>[orig_patent_app_number] => 11521270 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/521270
Computationally efficient design rule checking for circuit interconnect routing design Sep 12, 2006 Issued
Array ( [id] => 4706522 [patent_doc_number] => 20080066046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Hardware definition language generation for frame-based processing' [patent_app_type] => utility [patent_app_number] => 11/519290 [patent_app_country] => US [patent_app_date] => 2006-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 11434 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20080066046.pdf [firstpage_image] =>[orig_patent_app_number] => 11519290 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/519290
Hardware definition language generation for frame-based processing Sep 10, 2006 Issued
Array ( [id] => 5143902 [patent_doc_number] => 20070006118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Displacing Edge Segments On A Fabrication Layout Based On Proximity Effects Model Amplitudes For Correcting Proximity Effects' [patent_app_type] => utility [patent_app_number] => 11/530426 [patent_app_country] => US [patent_app_date] => 2006-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 17651 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20070006118.pdf [firstpage_image] =>[orig_patent_app_number] => 11530426 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/530426
Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects Sep 7, 2006 Issued
Array ( [id] => 5139018 [patent_doc_number] => 20070001234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Systems and methods for reducing IR-drop noise' [patent_app_type] => utility [patent_app_number] => 11/516996 [patent_app_country] => US [patent_app_date] => 2006-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3323 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20070001234.pdf [firstpage_image] =>[orig_patent_app_number] => 11516996 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/516996
Systems and methods for reducing IR-drop noise Sep 6, 2006 Issued
Array ( [id] => 146872 [patent_doc_number] => 07689955 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-30 [patent_title] => 'Register retiming technique' [patent_app_type] => utility [patent_app_number] => 11/513450 [patent_app_country] => US [patent_app_date] => 2006-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 14605 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/689/07689955.pdf [firstpage_image] =>[orig_patent_app_number] => 11513450 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/513450
Register retiming technique Aug 29, 2006 Issued
Array ( [id] => 302236 [patent_doc_number] => 07539955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-26 [patent_title] => 'System and method for reformatting a motherboard design file' [patent_app_type] => utility [patent_app_number] => 11/309520 [patent_app_country] => US [patent_app_date] => 2006-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1602 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/539/07539955.pdf [firstpage_image] =>[orig_patent_app_number] => 11309520 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/309520
System and method for reformatting a motherboard design file Aug 15, 2006 Issued
Array ( [id] => 4455131 [patent_doc_number] => 07966579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Methods of optical proximity correction' [patent_app_type] => utility [patent_app_number] => 11/499610 [patent_app_country] => US [patent_app_date] => 2006-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6897 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966579.pdf [firstpage_image] =>[orig_patent_app_number] => 11499610 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/499610
Methods of optical proximity correction Aug 3, 2006 Issued
Array ( [id] => 248925 [patent_doc_number] => 07587686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-08 [patent_title] => 'Clock gating in a structured ASIC' [patent_app_type] => utility [patent_app_number] => 11/497705 [patent_app_country] => US [patent_app_date] => 2006-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5294 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/587/07587686.pdf [firstpage_image] =>[orig_patent_app_number] => 11497705 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/497705
Clock gating in a structured ASIC Jul 31, 2006 Issued
Array ( [id] => 5734773 [patent_doc_number] => 20060259890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Method and apparatus for power consumption reduction' [patent_app_type] => utility [patent_app_number] => 11/486030 [patent_app_country] => US [patent_app_date] => 2006-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4535 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259890.pdf [firstpage_image] =>[orig_patent_app_number] => 11486030 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/486030
Apparatus for power consumption reduction Jul 13, 2006 Issued
Array ( [id] => 5206719 [patent_doc_number] => 20070028201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Enhanced routing grid system and method' [patent_app_type] => utility [patent_app_number] => 11/477078 [patent_app_country] => US [patent_app_date] => 2006-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11443 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20070028201.pdf [firstpage_image] =>[orig_patent_app_number] => 11477078 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/477078
Enhanced routing grid system and method Jun 27, 2006 Abandoned
Array ( [id] => 5604136 [patent_doc_number] => 20060294483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'STRUCTURALLY FIELD-CONFIGURABLE SEMICONDUCTOR ARRAY FOR IN-MEMORY PROCESSING OF STATEFUL, TRANSACTION-ORIENTED SYSTEMS' [patent_app_type] => utility [patent_app_number] => 11/426880 [patent_app_country] => US [patent_app_date] => 2006-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10407 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0294/20060294483.pdf [firstpage_image] =>[orig_patent_app_number] => 11426880 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426880
Structurally field-configurable semiconductor array for in-memory processing of stateful, transaction-oriented systems Jun 26, 2006 Issued
Array ( [id] => 5922008 [patent_doc_number] => 20060240342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Resolution enhancing technology using phase assignment bridges' [patent_app_type] => utility [patent_app_number] => 11/475480 [patent_app_country] => US [patent_app_date] => 2006-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5913 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20060240342.pdf [firstpage_image] =>[orig_patent_app_number] => 11475480 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/475480
Resolution enhancing technology using phase assignment bridges Jun 25, 2006 Issued
Array ( [id] => 284233 [patent_doc_number] => 07555736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Method and system for using pattern matching to process an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 11/453720 [patent_app_country] => US [patent_app_date] => 2006-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 3851 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/555/07555736.pdf [firstpage_image] =>[orig_patent_app_number] => 11453720 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/453720
Method and system for using pattern matching to process an integrated circuit design Jun 13, 2006 Issued
Array ( [id] => 248929 [patent_doc_number] => 07587690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-09-08 [patent_title] => 'Method and system for global coverage analysis' [patent_app_type] => utility [patent_app_number] => 11/454075 [patent_app_country] => US [patent_app_date] => 2006-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4995 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/587/07587690.pdf [firstpage_image] =>[orig_patent_app_number] => 11454075 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/454075
Method and system for global coverage analysis Jun 13, 2006 Issued
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