Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5229421 [patent_doc_number] => 20070291528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'Method and apparatus for improving SRAM cell stability by using boosted word lines' [patent_app_type] => utility [patent_app_number] => 11/450610 [patent_app_country] => US [patent_app_date] => 2006-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2761 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20070291528.pdf [firstpage_image] =>[orig_patent_app_number] => 11450610 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/450610
Method and apparatus for improving SRAM cell stability by using boosted word lines Jun 8, 2006 Issued
Array ( [id] => 555201 [patent_doc_number] => RE040597 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2008-12-02 [patent_title] => 'Evaluation TEG for semiconductor device and method of evaluation' [patent_app_type] => reissue [patent_app_number] => 11/449007 [patent_app_country] => US [patent_app_date] => 2006-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 6753 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040597.pdf [firstpage_image] =>[orig_patent_app_number] => 11449007 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/449007
Evaluation TEG for semiconductor device and method of evaluation Jun 7, 2006 Issued
Array ( [id] => 5663220 [patent_doc_number] => 20060253816 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Apparatus and Method For Memory Efficient, Programmable, Pattern Matching Finite State Machine Hardware' [patent_app_type] => utility [patent_app_number] => 11/422520 [patent_app_country] => US [patent_app_date] => 2006-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4504 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253816.pdf [firstpage_image] =>[orig_patent_app_number] => 11422520 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/422520
Apparatus and method for generating state transition rules for memory efficient programmable pattern matching finite state machine hardware Jun 5, 2006 Issued
Array ( [id] => 5701833 [patent_doc_number] => 20060218518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Semiconductor integrated device and apparatus for designing the same' [patent_app_type] => utility [patent_app_number] => 11/444617 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8796 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20060218518.pdf [firstpage_image] =>[orig_patent_app_number] => 11444617 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/444617
Semiconductor integrated device and apparatus for designing the same May 31, 2006 Issued
Array ( [id] => 4508902 [patent_doc_number] => 07958462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Computer-readable non-transitory medium storing three-dimensional device simulation program and three-dimensional device simulation system' [patent_app_type] => utility [patent_app_number] => 11/443200 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 4303 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/958/07958462.pdf [firstpage_image] =>[orig_patent_app_number] => 11443200 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/443200
Computer-readable non-transitory medium storing three-dimensional device simulation program and three-dimensional device simulation system May 30, 2006 Issued
Array ( [id] => 5024881 [patent_doc_number] => 20070150848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'UNALLOCATABLE SPACE DEPICTING SYSTEM AND METHOD FOR A COMPONENT ON A PRINTED CIRCUIT BOARD' [patent_app_type] => utility [patent_app_number] => 11/308920 [patent_app_country] => US [patent_app_date] => 2006-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2295 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20070150848.pdf [firstpage_image] =>[orig_patent_app_number] => 11308920 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/308920
Unallocatable space depicting system and method for a component on a printed circuit board May 24, 2006 Issued
Array ( [id] => 163556 [patent_doc_number] => 07676768 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-09 [patent_title] => 'Automatic asynchronous signal pipelining' [patent_app_type] => utility [patent_app_number] => 11/437950 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 7890 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676768.pdf [firstpage_image] =>[orig_patent_app_number] => 11437950 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/437950
Automatic asynchronous signal pipelining May 18, 2006 Issued
Array ( [id] => 5620586 [patent_doc_number] => 20060190120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Semiconductor manufacturing apparatus, management apparatus therefor, component management apparatus therefor, and semiconductor wafer storage vessel transport apparatus' [patent_app_type] => utility [patent_app_number] => 11/404754 [patent_app_country] => US [patent_app_date] => 2006-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 10671 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190120.pdf [firstpage_image] =>[orig_patent_app_number] => 11404754 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/404754
Semiconductor manufacturing apparatus, management apparatus therefor, component management apparatus therefor, and semiconductor wafer storage vessel transport apparatus Apr 16, 2006 Issued
Array ( [id] => 362954 [patent_doc_number] => 07487476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool' [patent_app_type] => utility [patent_app_number] => 11/279300 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4320 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487476.pdf [firstpage_image] =>[orig_patent_app_number] => 11279300 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/279300
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool Apr 10, 2006 Issued
Array ( [id] => 231644 [patent_doc_number] => 07603634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Various methods and apparatuses to preserve a logic state for a volatile latch circuit' [patent_app_type] => utility [patent_app_number] => 11/401806 [patent_app_country] => US [patent_app_date] => 2006-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7677 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/603/07603634.pdf [firstpage_image] =>[orig_patent_app_number] => 11401806 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/401806
Various methods and apparatuses to preserve a logic state for a volatile latch circuit Apr 9, 2006 Issued
Array ( [id] => 4592927 [patent_doc_number] => 07853903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-14 [patent_title] => 'Method and mechanism for performing simulation off resolution proof' [patent_app_type] => utility [patent_app_number] => 11/397230 [patent_app_country] => US [patent_app_date] => 2006-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5844 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853903.pdf [firstpage_image] =>[orig_patent_app_number] => 11397230 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/397230
Method and mechanism for performing simulation off resolution proof Apr 2, 2006 Issued
Array ( [id] => 5859153 [patent_doc_number] => 20060228912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Orthogonal backplane connector' [patent_app_type] => utility [patent_app_number] => 11/388549 [patent_app_country] => US [patent_app_date] => 2006-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 10577 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20060228912.pdf [firstpage_image] =>[orig_patent_app_number] => 11388549 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/388549
Orthogonal backplane connector Mar 23, 2006 Abandoned
Array ( [id] => 201060 [patent_doc_number] => 07640525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-29 [patent_title] => 'Assisting printed board design process' [patent_app_type] => utility [patent_app_number] => 11/377580 [patent_app_country] => US [patent_app_date] => 2006-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/640/07640525.pdf [firstpage_image] =>[orig_patent_app_number] => 11377580 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/377580
Assisting printed board design process Mar 16, 2006 Issued
Array ( [id] => 5696120 [patent_doc_number] => 20060156267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Recording medium recording a wiring method' [patent_app_type] => utility [patent_app_number] => 11/372150 [patent_app_country] => US [patent_app_date] => 2006-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9106 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156267.pdf [firstpage_image] =>[orig_patent_app_number] => 11372150 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/372150
Recording medium recording a wiring method Mar 9, 2006 Abandoned
Array ( [id] => 366809 [patent_doc_number] => 07484198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-27 [patent_title] => 'Managing integrated circuit stress using dummy diffusion regions' [patent_app_type] => utility [patent_app_number] => 11/364390 [patent_app_country] => US [patent_app_date] => 2006-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 12547 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/484/07484198.pdf [firstpage_image] =>[orig_patent_app_number] => 11364390 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/364390
Managing integrated circuit stress using dummy diffusion regions Feb 26, 2006 Issued
Array ( [id] => 305946 [patent_doc_number] => 07536661 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-19 [patent_title] => 'Incremental placement during physical synthesis' [patent_app_type] => utility [patent_app_number] => 11/361370 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5865 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/536/07536661.pdf [firstpage_image] =>[orig_patent_app_number] => 11361370 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/361370
Incremental placement during physical synthesis Feb 23, 2006 Issued
Array ( [id] => 5339320 [patent_doc_number] => 20090055784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'METHOD FOR VERIFYING SAFETY APPARATUS AND SAFETY APPARATUS VERIFIED BY THE SAME' [patent_app_type] => utility [patent_app_number] => 11/360617 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8576 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055784.pdf [firstpage_image] =>[orig_patent_app_number] => 11360617 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360617
Method for verifying safety apparatus and safety apparatus verified by the same Feb 23, 2006 Issued
Array ( [id] => 362984 [patent_doc_number] => 07487491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Pattern inspection system using image correction scheme with object-sensitive automatic mode switchability' [patent_app_type] => utility [patent_app_number] => 11/360580 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 8351 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/487/07487491.pdf [firstpage_image] =>[orig_patent_app_number] => 11360580 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360580
Pattern inspection system using image correction scheme with object-sensitive automatic mode switchability Feb 23, 2006 Issued
Array ( [id] => 336962 [patent_doc_number] => 07509595 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-24 [patent_title] => 'Method and system for enabling energy efficient wireless connectivity' [patent_app_type] => utility [patent_app_number] => 11/361501 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2691 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509595.pdf [firstpage_image] =>[orig_patent_app_number] => 11361501 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/361501
Method and system for enabling energy efficient wireless connectivity Feb 23, 2006 Issued
Array ( [id] => 5657850 [patent_doc_number] => 20060143586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-29 [patent_title] => 'Synthesis strategies based on the appropriate use of inductance effects' [patent_app_type] => utility [patent_app_number] => 11/359135 [patent_app_country] => US [patent_app_date] => 2006-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11102 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20060143586.pdf [firstpage_image] =>[orig_patent_app_number] => 11359135 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/359135
Synthesis strategies based on the appropriate use of inductance effects Feb 20, 2006 Issued
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