
Paul Dinh
Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2816, 2825 |
| Total Applications | 2030 |
| Issued Applications | 1783 |
| Pending Applications | 89 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5229421
[patent_doc_number] => 20070291528
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[patent_title] => 'Method and apparatus for improving SRAM cell stability by using boosted word lines'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/450610 | Method and apparatus for improving SRAM cell stability by using boosted word lines | Jun 8, 2006 | Issued |
Array
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[patent_issue_date] => 2008-12-02
[patent_title] => 'Evaluation TEG for semiconductor device and method of evaluation'
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Array
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[patent_issue_date] => 2006-11-09
[patent_title] => 'Apparatus and Method For Memory Efficient, Programmable, Pattern Matching Finite State Machine Hardware'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/422520 | Apparatus and method for generating state transition rules for memory efficient programmable pattern matching finite state machine hardware | Jun 5, 2006 | Issued |
Array
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[patent_issue_date] => 2006-09-28
[patent_title] => 'Semiconductor integrated device and apparatus for designing the same'
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Array
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[patent_title] => 'Computer-readable non-transitory medium storing three-dimensional device simulation program and three-dimensional device simulation system'
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Array
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[patent_title] => 'UNALLOCATABLE SPACE DEPICTING SYSTEM AND METHOD FOR A COMPONENT ON A PRINTED CIRCUIT BOARD'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/308920 | Unallocatable space depicting system and method for a component on a printed circuit board | May 24, 2006 | Issued |
Array
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[patent_title] => 'Automatic asynchronous signal pipelining'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/437950 | Automatic asynchronous signal pipelining | May 18, 2006 | Issued |
Array
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[patent_title] => 'Semiconductor manufacturing apparatus, management apparatus therefor, component management apparatus therefor, and semiconductor wafer storage vessel transport apparatus'
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Array
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[patent_title] => 'Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool'
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Array
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[patent_title] => 'Various methods and apparatuses to preserve a logic state for a volatile latch circuit'
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Array
(
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[patent_title] => 'Method and mechanism for performing simulation off resolution proof'
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Array
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Array
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Array
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Array
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Array
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