Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 582907 [patent_doc_number] => 07472372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-30 [patent_title] => 'Fast image simulation for photolithography' [patent_app_type] => utility [patent_app_number] => 11/269910 [patent_app_country] => US [patent_app_date] => 2005-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8364 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/472/07472372.pdf [firstpage_image] =>[orig_patent_app_number] => 11269910 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/269910
Fast image simulation for photolithography Nov 7, 2005 Issued
Array ( [id] => 5034774 [patent_doc_number] => 20070099313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Method of design based process control optimization' [patent_app_type] => utility [patent_app_number] => 11/265040 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2788 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20070099313.pdf [firstpage_image] =>[orig_patent_app_number] => 11265040 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/265040
Method of design based process control optimization Nov 1, 2005 Issued
Array ( [id] => 4789403 [patent_doc_number] => 20080290376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'Semiconductor Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 11/666760 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4836 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20080290376.pdf [firstpage_image] =>[orig_patent_app_number] => 11666760 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/666760
Semiconductor Integrated Circuit Oct 27, 2005 Abandoned
Array ( [id] => 856491 [patent_doc_number] => 07380227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-27 [patent_title] => 'Automated correction of asymmetric enclosure rule violations in a design layout' [patent_app_type] => utility [patent_app_number] => 11/261960 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 45 [patent_no_of_words] => 11257 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/380/07380227.pdf [firstpage_image] =>[orig_patent_app_number] => 11261960 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/261960
Automated correction of asymmetric enclosure rule violations in a design layout Oct 27, 2005 Issued
Array ( [id] => 5036769 [patent_doc_number] => 20070101308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-03 [patent_title] => 'Nanowire crossbar implementations of logic gates using configurable, tunneling resistor junctions' [patent_app_type] => utility [patent_app_number] => 11/262354 [patent_app_country] => US [patent_app_date] => 2005-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5550 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20070101308.pdf [firstpage_image] =>[orig_patent_app_number] => 11262354 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/262354
Nanowire crossbar implementations of logic gates using configurable, tunneling resistor junctions Oct 27, 2005 Issued
Array ( [id] => 5038119 [patent_doc_number] => 20070090401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-26 [patent_title] => 'I/O driver power distribution method for reducing silicon area' [patent_app_type] => utility [patent_app_number] => 11/254903 [patent_app_country] => US [patent_app_date] => 2005-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3972 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20070090401.pdf [firstpage_image] =>[orig_patent_app_number] => 11254903 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/254903
I/O driver power distribution method for reducing silicon area Oct 19, 2005 Issued
Array ( [id] => 5206720 [patent_doc_number] => 20070028202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'Method and apparatus for generating design information, and computer product' [patent_app_type] => utility [patent_app_number] => 11/251770 [patent_app_country] => US [patent_app_date] => 2005-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9020 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20070028202.pdf [firstpage_image] =>[orig_patent_app_number] => 11251770 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/251770
Method and apparatus for generating design information, and computer product Oct 17, 2005 Issued
Array ( [id] => 591053 [patent_doc_number] => 07464349 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-09 [patent_title] => 'Method and system or generating a current source model of a gate' [patent_app_type] => utility [patent_app_number] => 11/246060 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4540 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/464/07464349.pdf [firstpage_image] =>[orig_patent_app_number] => 11246060 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/246060
Method and system or generating a current source model of a gate Oct 10, 2005 Issued
Array ( [id] => 5195354 [patent_doc_number] => 20070083839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'On-the-fly RTL instructor for advanced DFT and design closure' [patent_app_type] => utility [patent_app_number] => 11/247630 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6549 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083839.pdf [firstpage_image] =>[orig_patent_app_number] => 11247630 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/247630
On-the-fly RTL instructor for advanced DFT and design closure Oct 10, 2005 Issued
Array ( [id] => 5195349 [patent_doc_number] => 20070083834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Method for sram bitmap verification' [patent_app_type] => utility [patent_app_number] => 11/246880 [patent_app_country] => US [patent_app_date] => 2005-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1442 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083834.pdf [firstpage_image] =>[orig_patent_app_number] => 11246880 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/246880
Method for SRAM bitmap verification Oct 6, 2005 Issued
Array ( [id] => 5195353 [patent_doc_number] => 20070083838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Generating a base curve database to reduce storage cost' [patent_app_type] => utility [patent_app_number] => 11/245550 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4947 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083838.pdf [firstpage_image] =>[orig_patent_app_number] => 11245550 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/245550
Generating a base curve database to reduce storage cost Oct 5, 2005 Issued
Array ( [id] => 5195358 [patent_doc_number] => 20070083843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-12 [patent_title] => 'Method, system and program product for providing a configuration specification language supporting error checking dials' [patent_app_type] => utility [patent_app_number] => 11/245300 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20070083843.pdf [firstpage_image] =>[orig_patent_app_number] => 11245300 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/245300
Method, system and program product for providing a configuration specification language supporting error checking dials Oct 5, 2005 Issued
Array ( [id] => 816697 [patent_doc_number] => 07415687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Method and computer program for incremental placement and routing with nested shells' [patent_app_type] => utility [patent_app_number] => 11/244530 [patent_app_country] => US [patent_app_date] => 2005-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4134 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/415/07415687.pdf [firstpage_image] =>[orig_patent_app_number] => 11244530 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/244530
Method and computer program for incremental placement and routing with nested shells Oct 4, 2005 Issued
Array ( [id] => 591037 [patent_doc_number] => 07464348 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-09 [patent_title] => 'Method and system for mapping source elements to destination elements as interconnect routing assignments' [patent_app_type] => utility [patent_app_number] => 11/239970 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3913 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/464/07464348.pdf [firstpage_image] =>[orig_patent_app_number] => 11239970 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/239970
Method and system for mapping source elements to destination elements as interconnect routing assignments Sep 29, 2005 Issued
Array ( [id] => 597176 [patent_doc_number] => 07454723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Validation of electrical performance of an electronic package prior to fabrication' [patent_app_type] => utility [patent_app_number] => 11/234560 [patent_app_country] => US [patent_app_date] => 2005-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 7416 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454723.pdf [firstpage_image] =>[orig_patent_app_number] => 11234560 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/234560
Validation of electrical performance of an electronic package prior to fabrication Sep 22, 2005 Issued
Array ( [id] => 898664 [patent_doc_number] => 07346885 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Method for producing a mask layout avoiding imaging errors for a mask' [patent_app_type] => utility [patent_app_number] => 11/233927 [patent_app_country] => US [patent_app_date] => 2005-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 8421 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/346/07346885.pdf [firstpage_image] =>[orig_patent_app_number] => 11233927 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/233927
Method for producing a mask layout avoiding imaging errors for a mask Sep 22, 2005 Issued
Array ( [id] => 594642 [patent_doc_number] => 07461359 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-02 [patent_title] => 'Method and mechanism for determining shape connectivity' [patent_app_type] => utility [patent_app_number] => 11/229344 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 34 [patent_no_of_words] => 10189 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/461/07461359.pdf [firstpage_image] =>[orig_patent_app_number] => 11229344 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/229344
Method and mechanism for determining shape connectivity Sep 14, 2005 Issued
Array ( [id] => 7589604 [patent_doc_number] => 07665045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-02-16 [patent_title] => 'Method and mechanism for identifying and tracking shape connectivity' [patent_app_type] => utility [patent_app_number] => 11/229320 [patent_app_country] => US [patent_app_date] => 2005-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 53 [patent_no_of_words] => 18708 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/665/07665045.pdf [firstpage_image] =>[orig_patent_app_number] => 11229320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/229320
Method and mechanism for identifying and tracking shape connectivity Sep 14, 2005 Issued
Array ( [id] => 600158 [patent_doc_number] => 07441212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-10-21 [patent_title] => 'State machine recognition and optimization' [patent_app_type] => utility [patent_app_number] => 11/222090 [patent_app_country] => US [patent_app_date] => 2005-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5889 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/441/07441212.pdf [firstpage_image] =>[orig_patent_app_number] => 11222090 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/222090
State machine recognition and optimization Sep 6, 2005 Issued
Array ( [id] => 5712011 [patent_doc_number] => 20060053357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Integrated circuit yield and quality analysis methods and systems' [patent_app_type] => utility [patent_app_number] => 11/221373 [patent_app_country] => US [patent_app_date] => 2005-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 33682 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20060053357.pdf [firstpage_image] =>[orig_patent_app_number] => 11221373 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/221373
Integrated circuit yield and quality analysis methods and systems Sep 5, 2005 Abandoned
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