Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5590146 [patent_doc_number] => 20060039597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Method for correcting a mask pattern, system for correcting a mask pattern, program, method for manufacturing a photomask and method for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/205180 [patent_app_country] => US [patent_app_date] => 2005-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 6968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20060039597.pdf [firstpage_image] =>[orig_patent_app_number] => 11205180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/205180
Method for correcting a mask pattern, system for correcting a mask pattern, program, method for manufacturing a photomask and method for manufacturing a semiconductor device Aug 16, 2005 Issued
Array ( [id] => 572362 [patent_doc_number] => 07469398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-23 [patent_title] => 'IP placement validation' [patent_app_type] => utility [patent_app_number] => 11/204670 [patent_app_country] => US [patent_app_date] => 2005-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4400 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/469/07469398.pdf [firstpage_image] =>[orig_patent_app_number] => 11204670 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/204670
IP placement validation Aug 15, 2005 Issued
Array ( [id] => 5053013 [patent_doc_number] => 20070033558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Method and system for reshaping metal wires in VLSI design' [patent_app_type] => utility [patent_app_number] => 11/199900 [patent_app_country] => US [patent_app_date] => 2005-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6734 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20070033558.pdf [firstpage_image] =>[orig_patent_app_number] => 11199900 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/199900
Method and system for reshaping metal wires in VLSI design Aug 7, 2005 Abandoned
Array ( [id] => 368881 [patent_doc_number] => 07480874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-20 [patent_title] => 'Reliability analysis of integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/198930 [patent_app_country] => US [patent_app_date] => 2005-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3747 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/480/07480874.pdf [firstpage_image] =>[orig_patent_app_number] => 11198930 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/198930
Reliability analysis of integrated circuits Aug 4, 2005 Issued
Array ( [id] => 329734 [patent_doc_number] => 07516427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Input capacitance characterization method in IP library' [patent_app_type] => utility [patent_app_number] => 11/197820 [patent_app_country] => US [patent_app_date] => 2005-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3173 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516427.pdf [firstpage_image] =>[orig_patent_app_number] => 11197820 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197820
Input capacitance characterization method in IP library Aug 4, 2005 Issued
Array ( [id] => 537637 [patent_doc_number] => 07191414 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-13 [patent_title] => 'Apparatus and methods for interconnect simulation in electronic circuitry using non-uniform time step' [patent_app_type] => utility [patent_app_number] => 11/196129 [patent_app_country] => US [patent_app_date] => 2005-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 9144 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191414.pdf [firstpage_image] =>[orig_patent_app_number] => 11196129 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196129
Apparatus and methods for interconnect simulation in electronic circuitry using non-uniform time step Aug 2, 2005 Issued
Array ( [id] => 5774472 [patent_doc_number] => 20050268262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'System and method for calculating effective capacitance for timing analysis' [patent_app_type] => utility [patent_app_number] => 11/195237 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6201 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20050268262.pdf [firstpage_image] =>[orig_patent_app_number] => 11195237 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/195237
System and method for calculating effective capacitance for timing analysis Aug 1, 2005 Issued
Array ( [id] => 5181219 [patent_doc_number] => 20070052562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-08 [patent_title] => 'Modular design method and apparatus' [patent_app_type] => utility [patent_app_number] => 11/191580 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1981 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20070052562.pdf [firstpage_image] =>[orig_patent_app_number] => 11191580 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/191580
Modular design method and apparatus Jul 27, 2005 Issued
Array ( [id] => 5822166 [patent_doc_number] => 20060026479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Verification vector creating method, and electronic circuit verifying method using the former method' [patent_app_type] => utility [patent_app_number] => 11/181017 [patent_app_country] => US [patent_app_date] => 2005-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7741 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026479.pdf [firstpage_image] =>[orig_patent_app_number] => 11181017 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/181017
Verification vector creating method, and electronic circuit verifying method using the former method Jul 13, 2005 Abandoned
Array ( [id] => 208731 [patent_doc_number] => 07631284 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-08 [patent_title] => 'Graphical user aid for technology migration and associated methods' [patent_app_type] => utility [patent_app_number] => 11/181110 [patent_app_country] => US [patent_app_date] => 2005-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3805 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/631/07631284.pdf [firstpage_image] =>[orig_patent_app_number] => 11181110 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/181110
Graphical user aid for technology migration and associated methods Jul 12, 2005 Issued
Array ( [id] => 7043771 [patent_doc_number] => 20050248366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Configurable logic and memory devices' [patent_app_type] => utility [patent_app_number] => 11/180936 [patent_app_country] => US [patent_app_date] => 2005-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3682 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20050248366.pdf [firstpage_image] =>[orig_patent_app_number] => 11180936 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/180936
Configurable logic and memory devices Jul 12, 2005 Issued
Array ( [id] => 5852946 [patent_doc_number] => 20060236137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-19 [patent_title] => 'Semiconductor device and method for designing the same' [patent_app_type] => utility [patent_app_number] => 11/175200 [patent_app_country] => US [patent_app_date] => 2005-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4166 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20060236137.pdf [firstpage_image] =>[orig_patent_app_number] => 11175200 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/175200
Semiconductor device and method for designing the same Jul 6, 2005 Issued
Array ( [id] => 5803314 [patent_doc_number] => 20060036774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-16 [patent_title] => 'System level applications of adaptive computing (SLAAC) technology' [patent_app_type] => utility [patent_app_number] => 11/175993 [patent_app_country] => US [patent_app_date] => 2005-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4543 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20060036774.pdf [firstpage_image] =>[orig_patent_app_number] => 11175993 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/175993
System level applications of adaptive computing (SLAAC) technology Jul 4, 2005 Issued
Array ( [id] => 5892563 [patent_doc_number] => 20060001100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Method for simulating electrostatic discharge protective circuit' [patent_app_type] => utility [patent_app_number] => 11/171200 [patent_app_country] => US [patent_app_date] => 2005-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5990 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20060001100.pdf [firstpage_image] =>[orig_patent_app_number] => 11171200 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/171200
Method for simulating electrostatic discharge protective circuit Jun 30, 2005 Abandoned
Array ( [id] => 5143889 [patent_doc_number] => 20070006105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Method and system for synthesis of flip-flops' [patent_app_type] => utility [patent_app_number] => 11/171160 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4008 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20070006105.pdf [firstpage_image] =>[orig_patent_app_number] => 11171160 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/171160
Method and system for synthesis of flip-flops Jun 29, 2005 Abandoned
Array ( [id] => 5896614 [patent_doc_number] => 20060005153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Device, method and program for estimating the number of layers of BGA component mounting substrate' [patent_app_type] => utility [patent_app_number] => 11/169584 [patent_app_country] => US [patent_app_date] => 2005-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5868 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20060005153.pdf [firstpage_image] =>[orig_patent_app_number] => 11169584 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/169584
Device, method and program for estimating the number of layers BGA component mounting substrate Jun 29, 2005 Issued
Array ( [id] => 4923873 [patent_doc_number] => 20080072190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Validating one or more circuits using one or more grids' [patent_app_type] => utility [patent_app_number] => 11/170470 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7434 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20080072190.pdf [firstpage_image] =>[orig_patent_app_number] => 11170470 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/170470
Validating one or more circuits using one of more grids Jun 27, 2005 Issued
Array ( [id] => 5698773 [patent_doc_number] => 20060215457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Method of generating cell library data for large scale integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/167280 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5240 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20060215457.pdf [firstpage_image] =>[orig_patent_app_number] => 11167280 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/167280
Method of generating cell library data for large scale integrated circuits Jun 27, 2005 Issued
Array ( [id] => 6975924 [patent_doc_number] => 20050285639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-29 [patent_title] => 'Integrated circuit with on-board power utilization information' [patent_app_type] => utility [patent_app_number] => 11/166830 [patent_app_country] => US [patent_app_date] => 2005-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7935 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20050285639.pdf [firstpage_image] =>[orig_patent_app_number] => 11166830 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/166830
Integrated circuit with on-board power utilization information Jun 23, 2005 Issued
Array ( [id] => 6927635 [patent_doc_number] => 20050240892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Suite of tools to design integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/156319 [patent_app_country] => US [patent_app_date] => 2005-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10383 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20050240892.pdf [firstpage_image] =>[orig_patent_app_number] => 11156319 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/156319
Suite of tools to design integrated circuits Jun 17, 2005 Issued
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