
Paul Dinh
Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2816, 2825 |
| Total Applications | 2030 |
| Issued Applications | 1783 |
| Pending Applications | 89 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5590146
[patent_doc_number] => 20060039597
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-23
[patent_title] => 'Method for correcting a mask pattern, system for correcting a mask pattern, program, method for manufacturing a photomask and method for manufacturing a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/205180
[patent_app_country] => US
[patent_app_date] => 2005-08-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0039/20060039597.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/205180 | Method for correcting a mask pattern, system for correcting a mask pattern, program, method for manufacturing a photomask and method for manufacturing a semiconductor device | Aug 16, 2005 | Issued |
Array
(
[id] => 572362
[patent_doc_number] => 07469398
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-12-23
[patent_title] => 'IP placement validation'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/204670 | IP placement validation | Aug 15, 2005 | Issued |
Array
(
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[patent_kind] => A1
[patent_issue_date] => 2007-02-08
[patent_title] => 'Method and system for reshaping metal wires in VLSI design'
[patent_app_type] => utility
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[patent_app_date] => 2005-08-08
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[firstpage_image] =>[orig_patent_app_number] => 11199900
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/199900 | Method and system for reshaping metal wires in VLSI design | Aug 7, 2005 | Abandoned |
Array
(
[id] => 368881
[patent_doc_number] => 07480874
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[patent_kind] => B2
[patent_issue_date] => 2009-01-20
[patent_title] => 'Reliability analysis of integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 11/198930
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/198930 | Reliability analysis of integrated circuits | Aug 4, 2005 | Issued |
Array
(
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[patent_issue_date] => 2009-04-07
[patent_title] => 'Input capacitance characterization method in IP library'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/197820 | Input capacitance characterization method in IP library | Aug 4, 2005 | Issued |
Array
(
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[patent_title] => 'Apparatus and methods for interconnect simulation in electronic circuitry using non-uniform time step'
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Array
(
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[patent_title] => 'System and method for calculating effective capacitance for timing analysis'
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[patent_app_country] => US
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Array
(
[id] => 5181219
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[patent_country] => US
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[patent_issue_date] => 2007-03-08
[patent_title] => 'Modular design method and apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/191580
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Array
(
[id] => 5822166
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[patent_title] => 'Verification vector creating method, and electronic circuit verifying method using the former method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/181017 | Verification vector creating method, and electronic circuit verifying method using the former method | Jul 13, 2005 | Abandoned |
Array
(
[id] => 208731
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[patent_title] => 'Graphical user aid for technology migration and associated methods'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/181110 | Graphical user aid for technology migration and associated methods | Jul 12, 2005 | Issued |
Array
(
[id] => 7043771
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Array
(
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Array
(
[id] => 5803314
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Array
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[patent_title] => 'Method for simulating electrostatic discharge protective circuit'
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Array
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Array
(
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Array
(
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Array
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Array
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