Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5773094 [patent_doc_number] => 20050267622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Synthesizing semiconductor process flow models' [patent_app_type] => utility [patent_app_number] => 11/153575 [patent_app_country] => US [patent_app_date] => 2005-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6104 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20050267622.pdf [firstpage_image] =>[orig_patent_app_number] => 11153575 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/153575
Synthesizing semiconductor process flow models Jun 13, 2005 Issued
Array ( [id] => 572324 [patent_doc_number] => 07469396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-23 [patent_title] => 'Semiconductor device and layout design method therefor' [patent_app_type] => utility [patent_app_number] => 11/149350 [patent_app_country] => US [patent_app_date] => 2005-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 36 [patent_no_of_words] => 12978 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/469/07469396.pdf [firstpage_image] =>[orig_patent_app_number] => 11149350 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/149350
Semiconductor device and layout design method therefor Jun 9, 2005 Issued
Array ( [id] => 5644348 [patent_doc_number] => 20060282803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Estimation of average-case activity for digital circuits' [patent_app_type] => utility [patent_app_number] => 11/149938 [patent_app_country] => US [patent_app_date] => 2005-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10623 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20060282803.pdf [firstpage_image] =>[orig_patent_app_number] => 11149938 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/149938
Estimation of average-case activity for digital circuits Jun 9, 2005 Issued
Array ( [id] => 6950270 [patent_doc_number] => 20050225364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'High speed low power input buffer' [patent_app_type] => utility [patent_app_number] => 11/148739 [patent_app_country] => US [patent_app_date] => 2005-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4760 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20050225364.pdf [firstpage_image] =>[orig_patent_app_number] => 11148739 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/148739
High speed low power input buffer Jun 8, 2005 Abandoned
Array ( [id] => 5642766 [patent_doc_number] => 20060281221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Enhanced routing grid system and method' [patent_app_type] => utility [patent_app_number] => 11/148911 [patent_app_country] => US [patent_app_date] => 2005-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8994 [patent_no_of_claims] => 81 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20060281221.pdf [firstpage_image] =>[orig_patent_app_number] => 11148911 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/148911
Enhanced routing grid system and method Jun 8, 2005 Abandoned
Array ( [id] => 829403 [patent_doc_number] => 07404161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Fullchip functional equivalency and physical verification' [patent_app_type] => utility [patent_app_number] => 11/147822 [patent_app_country] => US [patent_app_date] => 2005-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/404/07404161.pdf [firstpage_image] =>[orig_patent_app_number] => 11147822 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/147822
Fullchip functional equivalency and physical verification Jun 7, 2005 Issued
Array ( [id] => 895045 [patent_doc_number] => 07350169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-25 [patent_title] => 'Method and system for enhanced verification through structural target decomposition' [patent_app_type] => utility [patent_app_number] => 11/143330 [patent_app_country] => US [patent_app_date] => 2005-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8652 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/350/07350169.pdf [firstpage_image] =>[orig_patent_app_number] => 11143330 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/143330
Method and system for enhanced verification through structural target decomposition Jun 1, 2005 Issued
Array ( [id] => 5774466 [patent_doc_number] => 20050268257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Semiconductor integrated circuit, method for designing semiconductor integrated circuit and system for designing semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/141329 [patent_app_country] => US [patent_app_date] => 2005-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2904 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20050268257.pdf [firstpage_image] =>[orig_patent_app_number] => 11141329 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/141329
Semiconductor integrated circuit, method for designing semiconductor integrated circuit and system for designing semiconductor integrated circuit May 31, 2005 Issued
Array ( [id] => 5606145 [patent_doc_number] => 20060267661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Clock signal networks for structured ASIC devices' [patent_app_type] => utility [patent_app_number] => 11/141867 [patent_app_country] => US [patent_app_date] => 2005-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3879 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20060267661.pdf [firstpage_image] =>[orig_patent_app_number] => 11141867 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/141867
Clock signal networks for structured ASIC devices May 30, 2005 Issued
Array ( [id] => 5644359 [patent_doc_number] => 20060282814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Method for verifying and choosing lithography model' [patent_app_type] => utility [patent_app_number] => 11/141805 [patent_app_country] => US [patent_app_date] => 2005-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3809 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20060282814.pdf [firstpage_image] =>[orig_patent_app_number] => 11141805 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/141805
Method for verifying and choosing lithography model May 30, 2005 Issued
Array ( [id] => 5610378 [patent_doc_number] => 20060271894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-30 [patent_title] => 'Relative positioning of circuit elements in circuit design' [patent_app_type] => utility [patent_app_number] => 11/138590 [patent_app_country] => US [patent_app_date] => 2005-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12387 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20060271894.pdf [firstpage_image] =>[orig_patent_app_number] => 11138590 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/138590
Relative positioning of circuit elements in circuit design May 25, 2005 Issued
Array ( [id] => 396974 [patent_doc_number] => 07299439 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-20 [patent_title] => 'Assignment of I/O objects with multiple I/O standards to virtual I/O banks using integer linear programming' [patent_app_type] => utility [patent_app_number] => 11/135980 [patent_app_country] => US [patent_app_date] => 2005-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 6603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/299/07299439.pdf [firstpage_image] =>[orig_patent_app_number] => 11135980 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/135980
Assignment of I/O objects with multiple I/O standards to virtual I/O banks using integer linear programming May 23, 2005 Issued
Array ( [id] => 466391 [patent_doc_number] => 07243327 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-10 [patent_title] => 'Method for automatically routing connections between top side conductors and bottom side conductors of an integrated circuit package' [patent_app_type] => utility [patent_app_number] => 11/136036 [patent_app_country] => US [patent_app_date] => 2005-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 37 [patent_no_of_words] => 9528 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/243/07243327.pdf [firstpage_image] =>[orig_patent_app_number] => 11136036 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/136036
Method for automatically routing connections between top side conductors and bottom side conductors of an integrated circuit package May 22, 2005 Issued
Array ( [id] => 340602 [patent_doc_number] => 07506281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-03-17 [patent_title] => 'Two-pass method for implementing a flexible testbench' [patent_app_type] => utility [patent_app_number] => 11/131750 [patent_app_country] => US [patent_app_date] => 2005-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5988 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/506/07506281.pdf [firstpage_image] =>[orig_patent_app_number] => 11131750 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/131750
Two-pass method for implementing a flexible testbench May 17, 2005 Issued
Array ( [id] => 444652 [patent_doc_number] => 07260796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'Capacitance measurements for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/129656 [patent_app_country] => US [patent_app_date] => 2005-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4143 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/260/07260796.pdf [firstpage_image] =>[orig_patent_app_number] => 11129656 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/129656
Capacitance measurements for an integrated circuit May 12, 2005 Issued
Array ( [id] => 5292240 [patent_doc_number] => 20090024970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-22 [patent_title] => 'Floor plan evaluating method, floor plan correcting method, program, floor plan evaluating device, and floor plan creating device' [patent_app_type] => utility [patent_app_number] => 11/659110 [patent_app_country] => US [patent_app_date] => 2005-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8233 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20090024970.pdf [firstpage_image] =>[orig_patent_app_number] => 11659110 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/659110
Floor plan evaluating method, floor plan correcting method, program, floor plan evaluating device, and floor plan creating device May 11, 2005 Issued
Array ( [id] => 5734774 [patent_doc_number] => 20060259891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'System and method of generating an auto-wiring script' [patent_app_type] => utility [patent_app_number] => 11/125140 [patent_app_country] => US [patent_app_date] => 2005-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3054 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259891.pdf [firstpage_image] =>[orig_patent_app_number] => 11125140 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/125140
System and method of generating an auto-wiring script May 9, 2005 Abandoned
Array ( [id] => 908868 [patent_doc_number] => 07337422 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-26 [patent_title] => 'Programmably configurable logic-based macro' [patent_app_type] => utility [patent_app_number] => 11/126130 [patent_app_country] => US [patent_app_date] => 2005-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5819 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/337/07337422.pdf [firstpage_image] =>[orig_patent_app_number] => 11126130 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/126130
Programmably configurable logic-based macro May 9, 2005 Issued
Array ( [id] => 813529 [patent_doc_number] => 07418690 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-26 [patent_title] => 'Local searching techniques for technology mapping' [patent_app_type] => utility [patent_app_number] => 11/119070 [patent_app_country] => US [patent_app_date] => 2005-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/418/07418690.pdf [firstpage_image] =>[orig_patent_app_number] => 11119070 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/119070
Local searching techniques for technology mapping Apr 28, 2005 Issued
Array ( [id] => 832748 [patent_doc_number] => 07401302 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-15 [patent_title] => 'System on chip development with reconfigurable multi-project wafer technology' [patent_app_type] => utility [patent_app_number] => 11/119086 [patent_app_country] => US [patent_app_date] => 2005-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2768 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/401/07401302.pdf [firstpage_image] =>[orig_patent_app_number] => 11119086 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/119086
System on chip development with reconfigurable multi-project wafer technology Apr 28, 2005 Issued
Menu