Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7071291 [patent_doc_number] => 20050246676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/111720 [patent_app_country] => US [patent_app_date] => 2005-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8456 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20050246676.pdf [firstpage_image] =>[orig_patent_app_number] => 11111720 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/111720
Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit Apr 21, 2005 Issued
Array ( [id] => 5836658 [patent_doc_number] => 20060248490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'System and method for text based placement engine for custom circuit design' [patent_app_type] => utility [patent_app_number] => 11/109100 [patent_app_country] => US [patent_app_date] => 2005-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20060248490.pdf [firstpage_image] =>[orig_patent_app_number] => 11109100 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/109100
System and method for text based placement engine for custom circuit design Apr 18, 2005 Issued
Array ( [id] => 914820 [patent_doc_number] => 07331022 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-12 [patent_title] => 'Method and apparatus for automating pin assignments' [patent_app_type] => utility [patent_app_number] => 11/100686 [patent_app_country] => US [patent_app_date] => 2005-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4127 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/331/07331022.pdf [firstpage_image] =>[orig_patent_app_number] => 11100686 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/100686
Method and apparatus for automating pin assignments Apr 5, 2005 Issued
Array ( [id] => 5740026 [patent_doc_number] => 20060010417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Apparatus, method and program product for suppressing waviness of features to be printed using photolithographic systems' [patent_app_type] => utility [patent_app_number] => 11/092983 [patent_app_country] => US [patent_app_date] => 2005-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5172 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20060010417.pdf [firstpage_image] =>[orig_patent_app_number] => 11092983 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/092983
Apparatus, method and program product for suppressing waviness of features to be printed using photolithographic systems Mar 29, 2005 Issued
Array ( [id] => 914825 [patent_doc_number] => 07331024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-12 [patent_title] => 'Power-consumption calculation method and apparatus' [patent_app_type] => utility [patent_app_number] => 11/093148 [patent_app_country] => US [patent_app_date] => 2005-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7688 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/331/07331024.pdf [firstpage_image] =>[orig_patent_app_number] => 11093148 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/093148
Power-consumption calculation method and apparatus Mar 29, 2005 Issued
Array ( [id] => 171994 [patent_doc_number] => 07669162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Integrated power supply system analyzing system, integrated power supply system analyzing method, and multiplayer printed circuit board' [patent_app_type] => utility [patent_app_number] => 11/547200 [patent_app_country] => US [patent_app_date] => 2005-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5724 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/669/07669162.pdf [firstpage_image] =>[orig_patent_app_number] => 11547200 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/547200
Integrated power supply system analyzing system, integrated power supply system analyzing method, and multiplayer printed circuit board Mar 29, 2005 Issued
Array ( [id] => 5701231 [patent_doc_number] => 20060217916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-28 [patent_title] => 'Method for integrally checking chip and package substrate layouts for errors' [patent_app_type] => utility [patent_app_number] => 11/089108 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20060217916.pdf [firstpage_image] =>[orig_patent_app_number] => 11089108 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089108
Method for integrally checking chip and package substrate layouts for errors Mar 23, 2005 Issued
Array ( [id] => 820202 [patent_doc_number] => 07412674 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-12 [patent_title] => 'System and method for measuring progress for formal verification of a design using analysis region' [patent_app_type] => utility [patent_app_number] => 11/089851 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9890 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/412/07412674.pdf [firstpage_image] =>[orig_patent_app_number] => 11089851 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089851
System and method for measuring progress for formal verification of a design using analysis region Mar 23, 2005 Issued
Array ( [id] => 396978 [patent_doc_number] => 07299441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-20 [patent_title] => 'Method for improving efficiency in laying out electronic components' [patent_app_type] => utility [patent_app_number] => 11/088321 [patent_app_country] => US [patent_app_date] => 2005-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2428 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/299/07299441.pdf [firstpage_image] =>[orig_patent_app_number] => 11088321 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/088321
Method for improving efficiency in laying out electronic components Mar 22, 2005 Issued
Array ( [id] => 525935 [patent_doc_number] => 07197729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Method and apparatus for computing equivalent capacitance' [patent_app_type] => utility [patent_app_number] => 11/077239 [patent_app_country] => US [patent_app_date] => 2005-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4621 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/197/07197729.pdf [firstpage_image] =>[orig_patent_app_number] => 11077239 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/077239
Method and apparatus for computing equivalent capacitance Mar 8, 2005 Issued
Array ( [id] => 829432 [patent_doc_number] => 07404173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Intermediate layout for resolution enhancement in semiconductor fabrication' [patent_app_type] => utility [patent_app_number] => 11/074882 [patent_app_country] => US [patent_app_date] => 2005-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 6217 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/404/07404173.pdf [firstpage_image] =>[orig_patent_app_number] => 11074882 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/074882
Intermediate layout for resolution enhancement in semiconductor fabrication Mar 6, 2005 Issued
Array ( [id] => 825724 [patent_doc_number] => 07406668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-29 [patent_title] => 'Methods for producing mappings of logic suitable for FPGA and structured ASIC implementations' [patent_app_type] => utility [patent_app_number] => 11/072560 [patent_app_country] => US [patent_app_date] => 2005-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5602 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/406/07406668.pdf [firstpage_image] =>[orig_patent_app_number] => 11072560 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/072560
Methods for producing mappings of logic suitable for FPGA and structured ASIC implementations Mar 2, 2005 Issued
Array ( [id] => 7113123 [patent_doc_number] => 20050210435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Automated method for the hierarchical and selective insertion of dummy surfaces into the physical design of a multilayer integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/065280 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7904 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20050210435.pdf [firstpage_image] =>[orig_patent_app_number] => 11065280 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/065280
Automated method for the hierarchical and selective insertion of dummy surfaces into the physical design of a multilayer integrated circuit Feb 24, 2005 Issued
Array ( [id] => 5789033 [patent_doc_number] => 20060206739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Method and circuit for reducing leakage and increasing read stability in a memory device' [patent_app_type] => utility [patent_app_number] => 11/066402 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5068 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20060206739.pdf [firstpage_image] =>[orig_patent_app_number] => 11066402 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/066402
Method and circuit for reducing leakage and increasing read stability in a memory device Feb 24, 2005 Issued
Array ( [id] => 5621358 [patent_doc_number] => 20060190893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Logic cell layout architecture with shared boundary' [patent_app_type] => utility [patent_app_number] => 11/066712 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3575 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190893.pdf [firstpage_image] =>[orig_patent_app_number] => 11066712 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/066712
Logic cell layout architecture with shared boundary Feb 23, 2005 Abandoned
Array ( [id] => 5616946 [patent_doc_number] => 20060186478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Method for optimising transistor performance in integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/067200 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2782 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20060186478.pdf [firstpage_image] =>[orig_patent_app_number] => 11067200 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/067200
Method for optimising transistor performance in integrated circuits Feb 23, 2005 Issued
Array ( [id] => 905170 [patent_doc_number] => 07340693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'System for designing re-programmable digital hardware platforms' [patent_app_type] => utility [patent_app_number] => 11/066070 [patent_app_country] => US [patent_app_date] => 2005-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10162 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340693.pdf [firstpage_image] =>[orig_patent_app_number] => 11066070 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/066070
System for designing re-programmable digital hardware platforms Feb 23, 2005 Issued
Array ( [id] => 929678 [patent_doc_number] => 07315991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-01 [patent_title] => 'Compiling HLL into massively pipelined systems' [patent_app_type] => utility [patent_app_number] => 11/064401 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5898 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315991.pdf [firstpage_image] =>[orig_patent_app_number] => 11064401 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064401
Compiling HLL into massively pipelined systems Feb 22, 2005 Issued
Array ( [id] => 623523 [patent_doc_number] => 07143388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'Method of transforming software language constructs to functional hardware equivalents' [patent_app_type] => utility [patent_app_number] => 11/060024 [patent_app_country] => US [patent_app_date] => 2005-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8829 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143388.pdf [firstpage_image] =>[orig_patent_app_number] => 11060024 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/060024
Method of transforming software language constructs to functional hardware equivalents Feb 16, 2005 Issued
Array ( [id] => 597146 [patent_doc_number] => 07454720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Method for optimizing a layout of supply lines' [patent_app_type] => utility [patent_app_number] => 11/060220 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3705 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/454/07454720.pdf [firstpage_image] =>[orig_patent_app_number] => 11060220 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/060220
Method for optimizing a layout of supply lines Feb 15, 2005 Issued
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