Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 856477 [patent_doc_number] => 07380219 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-27 [patent_title] => 'Method and apparatus for implementing a circuit design for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/054862 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4279 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/380/07380219.pdf [firstpage_image] =>[orig_patent_app_number] => 11054862 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054862
Method and apparatus for implementing a circuit design for an integrated circuit Feb 9, 2005 Issued
Array ( [id] => 753541 [patent_doc_number] => 07028274 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-11 [patent_title] => 'RRAM backend flow' [patent_app_type] => utility [patent_app_number] => 11/054460 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2279 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/028/07028274.pdf [firstpage_image] =>[orig_patent_app_number] => 11054460 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054460
RRAM backend flow Feb 8, 2005 Issued
Array ( [id] => 407404 [patent_doc_number] => 07290229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Method and system for optimized handling of constraints during symbolic simulation' [patent_app_type] => utility [patent_app_number] => 11/050592 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6981 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/290/07290229.pdf [firstpage_image] =>[orig_patent_app_number] => 11050592 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/050592
Method and system for optimized handling of constraints during symbolic simulation Feb 2, 2005 Issued
Array ( [id] => 414982 [patent_doc_number] => 07284210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Method for reconfiguration of random biases in a synthesized design without recompilation' [patent_app_type] => utility [patent_app_number] => 11/050232 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5248 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/284/07284210.pdf [firstpage_image] =>[orig_patent_app_number] => 11050232 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/050232
Method for reconfiguration of random biases in a synthesized design without recompilation Feb 2, 2005 Issued
Array ( [id] => 5621347 [patent_doc_number] => 20060190882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'System and method for generating assertions using waveforms' [patent_app_type] => utility [patent_app_number] => 11/050212 [patent_app_country] => US [patent_app_date] => 2005-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190882.pdf [firstpage_image] =>[orig_patent_app_number] => 11050212 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/050212
System and method for generating assertions using waveforms Feb 2, 2005 Abandoned
Array ( [id] => 925154 [patent_doc_number] => 07320114 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-15 [patent_title] => 'Method and system for verification of soft error handling with application to CMT processors' [patent_app_type] => utility [patent_app_number] => 11/049990 [patent_app_country] => US [patent_app_date] => 2005-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3860 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/320/07320114.pdf [firstpage_image] =>[orig_patent_app_number] => 11049990 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/049990
Method and system for verification of soft error handling with application to CMT processors Feb 1, 2005 Issued
Array ( [id] => 898553 [patent_doc_number] => 07346867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-18 [patent_title] => 'Method for estimating propagation noise based on effective capacitance in an integrated circuit chip' [patent_app_type] => utility [patent_app_number] => 11/048422 [patent_app_country] => US [patent_app_date] => 2005-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8438 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/346/07346867.pdf [firstpage_image] =>[orig_patent_app_number] => 11048422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/048422
Method for estimating propagation noise based on effective capacitance in an integrated circuit chip Jan 31, 2005 Issued
Array ( [id] => 451434 [patent_doc_number] => 07254799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Method for allocating resources in heterogeneous nanowire crossbars having defective nanowire junctions' [patent_app_type] => utility [patent_app_number] => 11/047981 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 32 [patent_no_of_words] => 9204 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/254/07254799.pdf [firstpage_image] =>[orig_patent_app_number] => 11047981 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/047981
Method for allocating resources in heterogeneous nanowire crossbars having defective nanowire junctions Jan 30, 2005 Issued
Array ( [id] => 5338546 [patent_doc_number] => 20090055010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'Back annotation equipment, mask layout correcting equipment, back annotation method, program, recording medium, process for fabricating semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/597180 [patent_app_country] => US [patent_app_date] => 2005-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20090055010.pdf [firstpage_image] =>[orig_patent_app_number] => 11597180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/597180
Back annotation equipment, mask layout correcting equipment, back annotation method, program, recording medium, process for fabricating semiconductor integrated circuit Jan 24, 2005 Abandoned
Array ( [id] => 843834 [patent_doc_number] => 07392489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-24 [patent_title] => 'Methods and apparatus for implementing application specific processors' [patent_app_type] => utility [patent_app_number] => 11/040152 [patent_app_country] => US [patent_app_date] => 2005-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5925 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/392/07392489.pdf [firstpage_image] =>[orig_patent_app_number] => 11040152 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/040152
Methods and apparatus for implementing application specific processors Jan 19, 2005 Issued
Array ( [id] => 5621329 [patent_doc_number] => 20060190864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-24 [patent_title] => 'Efficient modeling of embedded memories in bounded memory checking' [patent_app_type] => utility [patent_app_number] => 11/037920 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10798 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20060190864.pdf [firstpage_image] =>[orig_patent_app_number] => 11037920 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/037920
Efficient modeling of embedded memories in bounded memory checking Jan 17, 2005 Issued
Array ( [id] => 490794 [patent_doc_number] => 07222324 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-22 [patent_title] => 'Method and system for providing placement based configurations in programmable logic devices' [patent_app_type] => utility [patent_app_number] => 11/036310 [patent_app_country] => US [patent_app_date] => 2005-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3087 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/222/07222324.pdf [firstpage_image] =>[orig_patent_app_number] => 11036310 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/036310
Method and system for providing placement based configurations in programmable logic devices Jan 13, 2005 Issued
Array ( [id] => 5696114 [patent_doc_number] => 20060156261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Design verification technique' [patent_app_type] => utility [patent_app_number] => 11/034420 [patent_app_country] => US [patent_app_date] => 2005-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4694 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156261.pdf [firstpage_image] =>[orig_patent_app_number] => 11034420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/034420
Impact checking technique Jan 10, 2005 Issued
Array ( [id] => 691253 [patent_doc_number] => 07080332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'SPICE simulation system for diode and method of simulation using the same' [patent_app_type] => utility [patent_app_number] => 11/024630 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 2731 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080332.pdf [firstpage_image] =>[orig_patent_app_number] => 11024630 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/024630
SPICE simulation system for diode and method of simulation using the same Dec 29, 2004 Issued
Array ( [id] => 7036571 [patent_doc_number] => 20050156121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Methods and devices for charge management for three-dimensional and color sensing' [patent_app_type] => utility [patent_app_number] => 11/028290 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 31734 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20050156121.pdf [firstpage_image] =>[orig_patent_app_number] => 11028290 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/028290
Method enabling a standard CMOS fab to produce an IC to sense three-dimensional information using augmented rules creating mask patterns not otherwise expressible with existing fab rules Dec 29, 2004 Issued
Array ( [id] => 536139 [patent_doc_number] => 07194713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Logic verification device, logic verification method, and computer product' [patent_app_type] => utility [patent_app_number] => 11/017730 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8615 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194713.pdf [firstpage_image] =>[orig_patent_app_number] => 11017730 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/017730
Logic verification device, logic verification method, and computer product Dec 21, 2004 Issued
Array ( [id] => 771694 [patent_doc_number] => 07010766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Parallel design processes for integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/018440 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 5057 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010766.pdf [firstpage_image] =>[orig_patent_app_number] => 11018440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018440
Parallel design processes for integrated circuits Dec 20, 2004 Issued
Array ( [id] => 536270 [patent_doc_number] => 07194722 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-20 [patent_title] => 'Cost-independent critically-based target location selection for combinatorial optimization' [patent_app_type] => utility [patent_app_number] => 11/009260 [patent_app_country] => US [patent_app_date] => 2004-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3498 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194722.pdf [firstpage_image] =>[orig_patent_app_number] => 11009260 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/009260
Cost-independent critically-based target location selection for combinatorial optimization Dec 8, 2004 Issued
Array ( [id] => 6907252 [patent_doc_number] => 20050102647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Method and program for supporting register-transfer-level design of semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/007891 [patent_app_country] => US [patent_app_date] => 2004-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7862 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20050102647.pdf [firstpage_image] =>[orig_patent_app_number] => 11007891 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/007891
Method and program for supporting register-transfer-level design of semiconductor integrated circuit Dec 7, 2004 Issued
Array ( [id] => 810186 [patent_doc_number] => 07421668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-09-02 [patent_title] => 'Meaningful visualization of properties independent of a circuit design' [patent_app_type] => utility [patent_app_number] => 11/007860 [patent_app_country] => US [patent_app_date] => 2004-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 7162 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/421/07421668.pdf [firstpage_image] =>[orig_patent_app_number] => 11007860 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/007860
Meaningful visualization of properties independent of a circuit design Dec 7, 2004 Issued
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