Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5847395 [patent_doc_number] => 20060123377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Interconnect integrity verification' [patent_app_type] => utility [patent_app_number] => 11/005690 [patent_app_country] => US [patent_app_date] => 2004-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4729 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20060123377.pdf [firstpage_image] =>[orig_patent_app_number] => 11005690 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/005690
Interconnect integrity verification Dec 6, 2004 Issued
Array ( [id] => 891034 [patent_doc_number] => 07353480 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-01 [patent_title] => 'Apparatus, system, and method for designing via pads having extended contours' [patent_app_type] => utility [patent_app_number] => 11/007560 [patent_app_country] => US [patent_app_date] => 2004-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5010 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/353/07353480.pdf [firstpage_image] =>[orig_patent_app_number] => 11007560 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/007560
Apparatus, system, and method for designing via pads having extended contours Dec 6, 2004 Issued
Array ( [id] => 423861 [patent_doc_number] => 07275222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Method, apparatus, and computer program product for enhancing a power distribution system in a ceramic integrated circuit package' [patent_app_type] => utility [patent_app_number] => 11/002686 [patent_app_country] => US [patent_app_date] => 2004-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8077 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/275/07275222.pdf [firstpage_image] =>[orig_patent_app_number] => 11002686 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/002686
Method, apparatus, and computer program product for enhancing a power distribution system in a ceramic integrated circuit package Dec 1, 2004 Issued
Array ( [id] => 5087079 [patent_doc_number] => 20070277130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-29 [patent_title] => 'System and method for architecture verification' [patent_app_type] => utility [patent_app_number] => 10/581800 [patent_app_country] => US [patent_app_date] => 2004-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 21877 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20070277130.pdf [firstpage_image] =>[orig_patent_app_number] => 10581800 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/581800
System and method for architecture verification Dec 1, 2004 Abandoned
Array ( [id] => 745493 [patent_doc_number] => 07036097 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'Method for designing a cascade of digital filters for use in controling an electrolysis cell' [patent_app_type] => utility [patent_app_number] => 10/999350 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3977 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/036/07036097.pdf [firstpage_image] =>[orig_patent_app_number] => 10999350 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999350
Method for designing a cascade of digital filters for use in controling an electrolysis cell Nov 29, 2004 Issued
Array ( [id] => 5615235 [patent_doc_number] => 20060117164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'RECONFIGURABLE ENVIRONMENTALLY ADAPTIVE COMPUTING' [patent_app_type] => utility [patent_app_number] => 10/999463 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6583 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20060117164.pdf [firstpage_image] =>[orig_patent_app_number] => 10999463 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999463
Reconfigurable environmentally adaptive computing Nov 29, 2004 Issued
Array ( [id] => 7099202 [patent_doc_number] => 20050131661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method and system for characterizing electronic circuitry' [patent_app_type] => utility [patent_app_number] => 11/000140 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5480 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20050131661.pdf [firstpage_image] =>[orig_patent_app_number] => 11000140 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000140
Method and system for characterizing electronic circuitry Nov 29, 2004 Issued
Array ( [id] => 7239121 [patent_doc_number] => 20050140389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Logic basic cell and logic basic cell arrangement' [patent_app_type] => utility [patent_app_number] => 10/995960 [patent_app_country] => US [patent_app_date] => 2004-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 18943 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20050140389.pdf [firstpage_image] =>[orig_patent_app_number] => 10995960 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/995960
Logic basic cell and logic basic cell arrangement Nov 21, 2004 Issued
Array ( [id] => 5794623 [patent_doc_number] => 20060015304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Method for generating and evaluating a table model for circuit simulation' [patent_app_type] => utility [patent_app_number] => 10/992140 [patent_app_country] => US [patent_app_date] => 2004-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8339 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20060015304.pdf [firstpage_image] =>[orig_patent_app_number] => 10992140 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/992140
Method for generating and evaluating a table model for circuit simulation Nov 17, 2004 Issued
Array ( [id] => 782481 [patent_doc_number] => 06996797 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-07 [patent_title] => 'Method for verification of resolution enhancement techniques and optical proximity correction in lithography' [patent_app_type] => utility [patent_app_number] => 10/904600 [patent_app_country] => US [patent_app_date] => 2004-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3765 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996797.pdf [firstpage_image] =>[orig_patent_app_number] => 10904600 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/904600
Method for verification of resolution enhancement techniques and optical proximity correction in lithography Nov 17, 2004 Issued
Array ( [id] => 7186223 [patent_doc_number] => 20050125764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Method for producing a mask layout avoiding imaging errors for a mask' [patent_app_type] => utility [patent_app_number] => 10/988440 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3933 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20050125764.pdf [firstpage_image] =>[orig_patent_app_number] => 10988440 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/988440
Method for producing a mask layout avoiding imaging errors for a mask Nov 11, 2004 Abandoned
Array ( [id] => 498681 [patent_doc_number] => 07216314 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-08 [patent_title] => 'Integrated circuit verification method' [patent_app_type] => utility [patent_app_number] => 10/987860 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 7271 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/216/07216314.pdf [firstpage_image] =>[orig_patent_app_number] => 10987860 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/987860
Integrated circuit verification method Nov 11, 2004 Issued
Array ( [id] => 7107660 [patent_doc_number] => 20050108666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Delta information design closure in integrated circuit fabrication' [patent_app_type] => utility [patent_app_number] => 10/984210 [patent_app_country] => US [patent_app_date] => 2004-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15182 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20050108666.pdf [firstpage_image] =>[orig_patent_app_number] => 10984210 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/984210
Delta information design closure integrated circuit fabrication Nov 7, 2004 Issued
Array ( [id] => 5749443 [patent_doc_number] => 20060112378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-25 [patent_title] => 'Architecture specific code' [patent_app_type] => utility [patent_app_number] => 10/982350 [patent_app_country] => US [patent_app_date] => 2004-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2597 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20060112378.pdf [firstpage_image] =>[orig_patent_app_number] => 10982350 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982350
Architecture specific code Nov 5, 2004 Issued
Array ( [id] => 836527 [patent_doc_number] => 07398508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Eigen decomposition based OPC model' [patent_app_type] => utility [patent_app_number] => 10/981750 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 13907 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/398/07398508.pdf [firstpage_image] =>[orig_patent_app_number] => 10981750 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/981750
Eigen decomposition based OPC model Nov 4, 2004 Issued
Array ( [id] => 469742 [patent_doc_number] => 07240301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'System and method to insert new pages with a schematic capture tool' [patent_app_type] => utility [patent_app_number] => 10/904310 [patent_app_country] => US [patent_app_date] => 2004-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 3087 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240301.pdf [firstpage_image] =>[orig_patent_app_number] => 10904310 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/904310
System and method to insert new pages with a schematic capture tool Nov 2, 2004 Issued
Array ( [id] => 5809468 [patent_doc_number] => 20060095824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Determining circuit behavior' [patent_app_type] => utility [patent_app_number] => 10/979010 [patent_app_country] => US [patent_app_date] => 2004-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9139 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20060095824.pdf [firstpage_image] =>[orig_patent_app_number] => 10979010 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/979010
Determining circuit behavior Oct 31, 2004 Abandoned
Array ( [id] => 340643 [patent_doc_number] => 07506299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-17 [patent_title] => 'Feature optimization using interference mapping lithography' [patent_app_type] => utility [patent_app_number] => 10/975342 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 65 [patent_no_of_words] => 9106 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/506/07506299.pdf [firstpage_image] =>[orig_patent_app_number] => 10975342 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/975342
Feature optimization using interference mapping lithography Oct 28, 2004 Issued
Array ( [id] => 431597 [patent_doc_number] => 07269819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Method and apparatus for generating exposure data' [patent_app_type] => utility [patent_app_number] => 10/973270 [patent_app_country] => US [patent_app_date] => 2004-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6214 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269819.pdf [firstpage_image] =>[orig_patent_app_number] => 10973270 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/973270
Method and apparatus for generating exposure data Oct 26, 2004 Issued
Array ( [id] => 537702 [patent_doc_number] => 07191420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Net/wiring selection method, net selection method, wiring selection method, and delay improvement method' [patent_app_type] => utility [patent_app_number] => 10/972660 [patent_app_country] => US [patent_app_date] => 2004-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 10017 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191420.pdf [firstpage_image] =>[orig_patent_app_number] => 10972660 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/972660
Net/wiring selection method, net selection method, wiring selection method, and delay improvement method Oct 25, 2004 Issued
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