
Paul Dinh
Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2816, 2825 |
| Total Applications | 2030 |
| Issued Applications | 1783 |
| Pending Applications | 89 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5896613
[patent_doc_number] => 20060005152
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-05
[patent_title] => 'Method and device for designing semiconductor integrated circuit and logic design program'
[patent_app_type] => utility
[patent_app_number] => 10/968110
[patent_app_country] => US
[patent_app_date] => 2004-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5124
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0005/20060005152.pdf
[firstpage_image] =>[orig_patent_app_number] => 10968110
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/968110 | Method and device for designing semiconductor integrated circuit and logic design program | Oct 19, 2004 | Issued |
Array
(
[id] => 7119040
[patent_doc_number] => 20050071787
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-31
[patent_title] => 'Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of ASIC and programmable logic device'
[patent_app_type] => utility
[patent_app_number] => 10/965850
[patent_app_country] => US
[patent_app_date] => 2004-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 38
[patent_no_of_words] => 22871
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20050071787.pdf
[firstpage_image] =>[orig_patent_app_number] => 10965850
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/965850 | Development method for integrated circuits, program storage medium for storing the development method for integrated circuits, and concurrent development system, development program, and development method of ASIC and programmable logic device | Oct 17, 2004 | Issued |
Array
(
[id] => 5770637
[patent_doc_number] => 20050266495
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-12-01
[patent_title] => 'Method and program for library generation'
[patent_app_type] => utility
[patent_app_number] => 10/963730
[patent_app_country] => US
[patent_app_date] => 2004-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7216
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0266/20050266495.pdf
[firstpage_image] =>[orig_patent_app_number] => 10963730
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/963730 | Method and program for library generation | Oct 13, 2004 | Issued |
Array
(
[id] => 550717
[patent_doc_number] => 07185304
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-02-27
[patent_title] => 'System and method for VLSI CAD design'
[patent_app_type] => utility
[patent_app_number] => 10/965644
[patent_app_country] => US
[patent_app_date] => 2004-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 21
[patent_no_of_words] => 3394
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/185/07185304.pdf
[firstpage_image] =>[orig_patent_app_number] => 10965644
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/965644 | System and method for VLSI CAD design | Oct 13, 2004 | Issued |
Array
(
[id] => 7246776
[patent_doc_number] => 20050081176
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => 'Semiconductor device, routing method and manufacturing method of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/960720
[patent_app_country] => US
[patent_app_date] => 2004-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7001
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0081/20050081176.pdf
[firstpage_image] =>[orig_patent_app_number] => 10960720
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/960720 | Semiconductor device, routing method and manufacturing method of semiconductor device | Oct 7, 2004 | Issued |
Array
(
[id] => 458367
[patent_doc_number] => 07249331
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-24
[patent_title] => 'Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores'
[patent_app_type] => utility
[patent_app_number] => 10/960730
[patent_app_country] => US
[patent_app_date] => 2004-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4540
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/249/07249331.pdf
[firstpage_image] =>[orig_patent_app_number] => 10960730
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/960730 | Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores | Oct 6, 2004 | Issued |
Array
(
[id] => 400776
[patent_doc_number] => 07296249
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-13
[patent_title] => 'Using constrained scan cells to test integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/961760
[patent_app_country] => US
[patent_app_date] => 2004-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 18
[patent_no_of_words] => 13354
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/296/07296249.pdf
[firstpage_image] =>[orig_patent_app_number] => 10961760
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/961760 | Using constrained scan cells to test integrated circuits | Oct 6, 2004 | Issued |
Array
(
[id] => 623491
[patent_doc_number] => 07143372
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-11-28
[patent_title] => 'Apparatus measuring system-on-a-chip efficiency and method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/959050
[patent_app_country] => US
[patent_app_date] => 2004-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2619
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/143/07143372.pdf
[firstpage_image] =>[orig_patent_app_number] => 10959050
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/959050 | Apparatus measuring system-on-a-chip efficiency and method thereof | Oct 6, 2004 | Issued |
Array
(
[id] => 415020
[patent_doc_number] => 07284226
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-10-16
[patent_title] => 'Methods and structures of providing modular integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/956544
[patent_app_country] => US
[patent_app_date] => 2004-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 15
[patent_no_of_words] => 6895
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/284/07284226.pdf
[firstpage_image] =>[orig_patent_app_number] => 10956544
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/956544 | Methods and structures of providing modular integrated circuits | Sep 30, 2004 | Issued |
Array
(
[id] => 6944915
[patent_doc_number] => 20050196964
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-08
[patent_title] => 'Dummy fill for integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/947195
[patent_app_country] => US
[patent_app_date] => 2004-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 42
[patent_no_of_words] => 16728
[patent_no_of_claims] => 75
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0196/20050196964.pdf
[firstpage_image] =>[orig_patent_app_number] => 10947195
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/947195 | Dummy fill for integrated circuits | Sep 21, 2004 | Issued |
Array
(
[id] => 6971812
[patent_doc_number] => 20050037522
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-17
[patent_title] => 'Dummy fill for integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/946810
[patent_app_country] => US
[patent_app_date] => 2004-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 42
[patent_no_of_words] => 16727
[patent_no_of_claims] => 75
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0037/20050037522.pdf
[firstpage_image] =>[orig_patent_app_number] => 10946810
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/946810 | Dummy fill for integrated circuits | Sep 21, 2004 | Issued |
Array
(
[id] => 7198321
[patent_doc_number] => 20050051809
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-10
[patent_title] => 'Dummy fill for integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/947500
[patent_app_country] => US
[patent_app_date] => 2004-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 42
[patent_no_of_words] => 16716
[patent_no_of_claims] => 78
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0051/20050051809.pdf
[firstpage_image] =>[orig_patent_app_number] => 10947500
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/947500 | Dummy fill for integrated circuits | Sep 21, 2004 | Issued |
Array
(
[id] => 7605578
[patent_doc_number] => 07100145
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-29
[patent_title] => 'Method of identifying an extreme interaction pitch region, methods of designing mask patterns and manufacturing masks, device manufacturing methods and computer programs'
[patent_app_type] => utility
[patent_app_number] => 10/938510
[patent_app_country] => US
[patent_app_date] => 2004-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 27
[patent_no_of_words] => 9207
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/100/07100145.pdf
[firstpage_image] =>[orig_patent_app_number] => 10938510
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/938510 | Method of identifying an extreme interaction pitch region, methods of designing mask patterns and manufacturing masks, device manufacturing methods and computer programs | Sep 12, 2004 | Issued |
Array
(
[id] => 630049
[patent_doc_number] => 07137089
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-11-14
[patent_title] => 'Systems and methods for reducing IR-drop noise'
[patent_app_type] => utility
[patent_app_number] => 10/932220
[patent_app_country] => US
[patent_app_date] => 2004-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3304
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/137/07137089.pdf
[firstpage_image] =>[orig_patent_app_number] => 10932220
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/932220 | Systems and methods for reducing IR-drop noise | Aug 31, 2004 | Issued |
Array
(
[id] => 637692
[patent_doc_number] => 07131091
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-10-31
[patent_title] => 'Generating fast logic simulation models for a PLD design description'
[patent_app_type] => utility
[patent_app_number] => 10/930430
[patent_app_country] => US
[patent_app_date] => 2004-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4433
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/131/07131091.pdf
[firstpage_image] =>[orig_patent_app_number] => 10930430
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/930430 | Generating fast logic simulation models for a PLD design description | Aug 30, 2004 | Issued |
Array
(
[id] => 869142
[patent_doc_number] => 07370306
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-06
[patent_title] => 'Method and apparatus for designing a pattern on a semiconductor surface'
[patent_app_type] => utility
[patent_app_number] => 10/931361
[patent_app_country] => US
[patent_app_date] => 2004-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 7009
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/370/07370306.pdf
[firstpage_image] =>[orig_patent_app_number] => 10931361
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/931361 | Method and apparatus for designing a pattern on a semiconductor surface | Aug 30, 2004 | Issued |
Array
(
[id] => 5907454
[patent_doc_number] => 20060048089
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'System and method for simulating an aerial image'
[patent_app_type] => utility
[patent_app_number] => 10/928390
[patent_app_country] => US
[patent_app_date] => 2004-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5846
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0048/20060048089.pdf
[firstpage_image] =>[orig_patent_app_number] => 10928390
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/928390 | System and method for simulating an aerial image | Aug 26, 2004 | Issued |
Array
(
[id] => 7160941
[patent_doc_number] => 20050028119
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-02-03
[patent_title] => 'Vectorless instantaneous current estimation'
[patent_app_type] => utility
[patent_app_number] => 10/926660
[patent_app_country] => US
[patent_app_date] => 2004-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4953
[patent_no_of_claims] => 41
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0028/20050028119.pdf
[firstpage_image] =>[orig_patent_app_number] => 10926660
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/926660 | Vectorless instantaneous current estimation | Aug 24, 2004 | Issued |
Array
(
[id] => 676437
[patent_doc_number] => 07093213
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-15
[patent_title] => 'Method for designing an integrated circuit defect monitor'
[patent_app_type] => utility
[patent_app_number] => 10/710940
[patent_app_country] => US
[patent_app_date] => 2004-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 16
[patent_no_of_words] => 6977
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/093/07093213.pdf
[firstpage_image] =>[orig_patent_app_number] => 10710940
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/710940 | Method for designing an integrated circuit defect monitor | Aug 12, 2004 | Issued |
Array
(
[id] => 6954027
[patent_doc_number] => 20050229122
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'Logic verification device, logic verification method and logic verification computer program'
[patent_app_type] => utility
[patent_app_number] => 10/915608
[patent_app_country] => US
[patent_app_date] => 2004-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8410
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0229/20050229122.pdf
[firstpage_image] =>[orig_patent_app_number] => 10915608
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/915608 | Logic verification device, logic verification method and logic verification computer program | Aug 10, 2004 | Issued |