Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 619931 [patent_doc_number] => 07146583 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-05 [patent_title] => 'Method and system for implementing a circuit design in a tree representation' [patent_app_type] => utility [patent_app_number] => 10/912999 [patent_app_country] => US [patent_app_date] => 2004-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 7435 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/146/07146583.pdf [firstpage_image] =>[orig_patent_app_number] => 10912999 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/912999
Method and system for implementing a circuit design in a tree representation Aug 5, 2004 Issued
Array ( [id] => 882641 [patent_doc_number] => 07360177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-15 [patent_title] => 'Method and arrangement providing for implementation granularity using implementation sets' [patent_app_type] => utility [patent_app_number] => 10/913000 [patent_app_country] => US [patent_app_date] => 2004-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5371 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/360/07360177.pdf [firstpage_image] =>[orig_patent_app_number] => 10913000 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/913000
Method and arrangement providing for implementation granularity using implementation sets Aug 5, 2004 Issued
Array ( [id] => 7194200 [patent_doc_number] => 20050193354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-01 [patent_title] => 'Method of extraction of wire capacitances in LSI device having diagonal wires and extraction program for same' [patent_app_type] => utility [patent_app_number] => 10/898960 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6677 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20050193354.pdf [firstpage_image] =>[orig_patent_app_number] => 10898960 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/898960
Method of extraction of wire capacitances in LSI device having diagonal wires and extraction program for same Jul 26, 2004 Issued
Array ( [id] => 5822225 [patent_doc_number] => 20060026538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Relational database storage and retrieval of circuit element classifications' [patent_app_type] => utility [patent_app_number] => 11/089560 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8845 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20060026538.pdf [firstpage_image] =>[orig_patent_app_number] => 11089560 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089560
Relational database storage and retrieval of circuit element classifications Jul 26, 2004 Abandoned
Array ( [id] => 5881882 [patent_doc_number] => 20060030965 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Method and apparatus for automating VLSI modifications made after routing has been performed' [patent_app_type] => utility [patent_app_number] => 10/895170 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3591 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20060030965.pdf [firstpage_image] =>[orig_patent_app_number] => 10895170 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/895170
Method and apparatus for automating VLSI modifications made after routing has been performed Jul 19, 2004 Abandoned
Array ( [id] => 329728 [patent_doc_number] => 07516423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-07 [patent_title] => 'Method and apparatus for designing electronic circuits using optimization' [patent_app_type] => utility [patent_app_number] => 10/890349 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 11 [patent_no_of_words] => 11381 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/516/07516423.pdf [firstpage_image] =>[orig_patent_app_number] => 10890349 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/890349
Method and apparatus for designing electronic circuits using optimization Jul 12, 2004 Issued
Array ( [id] => 537680 [patent_doc_number] => 07191418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration' [patent_app_type] => utility [patent_app_number] => 10/889510 [patent_app_country] => US [patent_app_date] => 2004-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3898 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/191/07191418.pdf [firstpage_image] =>[orig_patent_app_number] => 10889510 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889510
Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration Jul 11, 2004 Issued
Array ( [id] => 5739795 [patent_doc_number] => 20060010186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'System and method for design and implementation of integrated-circuit digital filters' [patent_app_type] => utility [patent_app_number] => 10/884200 [patent_app_country] => US [patent_app_date] => 2004-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2968 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20060010186.pdf [firstpage_image] =>[orig_patent_app_number] => 10884200 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/884200
System and method for design and implementation of integrated-circuit digital filters Jul 5, 2004 Issued
Array ( [id] => 5892906 [patent_doc_number] => 20060001444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Application-specific integrated circuit equivalents of programmable logic and associated methods' [patent_app_type] => utility [patent_app_number] => 10/884460 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8357 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20060001444.pdf [firstpage_image] =>[orig_patent_app_number] => 10884460 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/884460
Application-specific integrated circuit equivalents of programmable logic and associated methods Jul 1, 2004 Issued
Array ( [id] => 762233 [patent_doc_number] => 07020854 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Automated processor generation system for designing a configurable processor and method for the same' [patent_app_type] => utility [patent_app_number] => 10/884590 [patent_app_country] => US [patent_app_date] => 2004-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 22665 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/020/07020854.pdf [firstpage_image] =>[orig_patent_app_number] => 10884590 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/884590
Automated processor generation system for designing a configurable processor and method for the same Jul 1, 2004 Issued
Array ( [id] => 860606 [patent_doc_number] => 07376930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-20 [patent_title] => 'Method, program product and apparatus for generating assist features utilizing an image field map' [patent_app_type] => utility [patent_app_number] => 10/878490 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 6957 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/376/07376930.pdf [firstpage_image] =>[orig_patent_app_number] => 10878490 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878490
Method, program product and apparatus for generating assist features utilizing an image field map Jun 28, 2004 Issued
Array ( [id] => 630059 [patent_doc_number] => 07137097 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-14 [patent_title] => 'Constraint-based global router for routing high performance designs' [patent_app_type] => utility [patent_app_number] => 10/877259 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 13227 [patent_no_of_claims] => 88 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/137/07137097.pdf [firstpage_image] =>[orig_patent_app_number] => 10877259 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877259
Constraint-based global router for routing high performance designs Jun 24, 2004 Issued
Array ( [id] => 922293 [patent_doc_number] => 07325220 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-29 [patent_title] => 'Techniques for automatically recommending a suitable programmable IC for a circuit design' [patent_app_type] => utility [patent_app_number] => 10/876035 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3259 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/325/07325220.pdf [firstpage_image] =>[orig_patent_app_number] => 10876035 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876035
Techniques for automatically recommending a suitable programmable IC for a circuit design Jun 22, 2004 Issued
Array ( [id] => 536264 [patent_doc_number] => 07194721 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-20 [patent_title] => 'Cost-independent criticality-based move selection for simulated annealing' [patent_app_type] => utility [patent_app_number] => 10/868956 [patent_app_country] => US [patent_app_date] => 2004-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2764 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/194/07194721.pdf [firstpage_image] =>[orig_patent_app_number] => 10868956 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/868956
Cost-independent criticality-based move selection for simulated annealing Jun 14, 2004 Issued
Array ( [id] => 7605585 [patent_doc_number] => 07100138 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Method and apparatus for circuit design' [patent_app_type] => utility [patent_app_number] => 10/863333 [patent_app_country] => US [patent_app_date] => 2004-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6481 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/100/07100138.pdf [firstpage_image] =>[orig_patent_app_number] => 10863333 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/863333
Method and apparatus for circuit design Jun 8, 2004 Issued
Array ( [id] => 823616 [patent_doc_number] => 07409652 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-05 [patent_title] => 'Debuggable opaque IP' [patent_app_type] => utility [patent_app_number] => 10/861893 [patent_app_country] => US [patent_app_date] => 2004-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7156 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/409/07409652.pdf [firstpage_image] =>[orig_patent_app_number] => 10861893 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/861893
Debuggable opaque IP Jun 3, 2004 Issued
Array ( [id] => 7030950 [patent_doc_number] => 20050022148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Semiconductor device layout method, a computer program, and a semiconductor device manufacture method' [patent_app_type] => utility [patent_app_number] => 10/861260 [patent_app_country] => US [patent_app_date] => 2004-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2913 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20050022148.pdf [firstpage_image] =>[orig_patent_app_number] => 10861260 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/861260
Semiconductor device layout method, a computer program, and a semiconductor device manufacture method Jun 3, 2004 Issued
Array ( [id] => 582875 [patent_doc_number] => 07472369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-30 [patent_title] => 'Embedding identification information on programmable devices' [patent_app_type] => utility [patent_app_number] => 10/861990 [patent_app_country] => US [patent_app_date] => 2004-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6137 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/472/07472369.pdf [firstpage_image] =>[orig_patent_app_number] => 10861990 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/861990
Embedding identification information on programmable devices Jun 2, 2004 Issued
Array ( [id] => 469754 [patent_doc_number] => 07240305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'OPC conflict identification and edge priority system' [patent_app_type] => utility [patent_app_number] => 10/859920 [patent_app_country] => US [patent_app_date] => 2004-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3123 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240305.pdf [firstpage_image] =>[orig_patent_app_number] => 10859920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/859920
OPC conflict identification and edge priority system Jun 1, 2004 Issued
Array ( [id] => 4591300 [patent_doc_number] => 07827511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Power distribution network of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/559913 [patent_app_country] => US [patent_app_date] => 2004-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/827/07827511.pdf [firstpage_image] =>[orig_patent_app_number] => 10559913 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/559913
Power distribution network of an integrated circuit May 31, 2004 Issued
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