
Paul Dinh
Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2816, 2825 |
| Total Applications | 2030 |
| Issued Applications | 1783 |
| Pending Applications | 89 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 705943
[patent_doc_number] => 07069522
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[patent_issue_date] => 2006-06-27
[patent_title] => 'Various methods and apparatuses to preserve a logic state for a volatile latch circuit'
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Array
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Array
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Array
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[patent_title] => 'Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit'
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Array
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[patent_title] => 'Systems, methods, and apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks'
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Array
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[patent_title] => 'Use of non-lithographic shrink techniques for fabrication/making of imprints masks'
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Array
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[patent_title] => 'Method and system for false path analysis'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/836700 | Method and system for false path analysis | Apr 28, 2004 | Issued |
Array
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[patent_title] => 'Delay estimation using edge specific miller capacitances'
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Array
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Array
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[patent_title] => 'Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device'
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Array
(
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Array
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Array
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Array
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Array
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