Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 705943 [patent_doc_number] => 07069522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-27 [patent_title] => 'Various methods and apparatuses to preserve a logic state for a volatile latch circuit' [patent_app_type] => utility [patent_app_number] => 10/856520 [patent_app_country] => US [patent_app_date] => 2004-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7599 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/069/07069522.pdf [firstpage_image] =>[orig_patent_app_number] => 10856520 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/856520
Various methods and apparatuses to preserve a logic state for a volatile latch circuit May 27, 2004 Issued
Array ( [id] => 782478 [patent_doc_number] => 06996796 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-07 [patent_title] => 'Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)' [patent_app_type] => utility [patent_app_number] => 10/847704 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/996/06996796.pdf [firstpage_image] =>[orig_patent_app_number] => 10847704 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/847704
Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC) May 17, 2004 Issued
Array ( [id] => 288686 [patent_doc_number] => 07552415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-23 [patent_title] => 'Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)' [patent_app_type] => utility [patent_app_number] => 10/848084 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5609 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/552/07552415.pdf [firstpage_image] =>[orig_patent_app_number] => 10848084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/848084
Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC) May 17, 2004 Issued
Array ( [id] => 641389 [patent_doc_number] => 07127694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/842210 [patent_app_country] => US [patent_app_date] => 2004-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 71 [patent_figures_cnt] => 99 [patent_no_of_words] => 22475 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/127/07127694.pdf [firstpage_image] =>[orig_patent_app_number] => 10842210 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/842210
Computer implemented design system, a computer implemented design method, a reticle set, and an integrated circuit May 9, 2004 Issued
Array ( [id] => 813517 [patent_doc_number] => 07418684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-08-26 [patent_title] => 'Systems, methods, and apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks' [patent_app_type] => utility [patent_app_number] => 10/841000 [patent_app_country] => US [patent_app_date] => 2004-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4202 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/418/07418684.pdf [firstpage_image] =>[orig_patent_app_number] => 10841000 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/841000
Systems, methods, and apparatus to perform static timing analysis and optimization for multi-mode clock circuit networks May 6, 2004 Issued
Array ( [id] => 583371 [patent_doc_number] => 07159205 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-01-02 [patent_title] => 'Use of non-lithographic shrink techniques for fabrication/making of imprints masks' [patent_app_type] => utility [patent_app_number] => 10/838830 [patent_app_country] => US [patent_app_date] => 2004-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 7839 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/159/07159205.pdf [firstpage_image] =>[orig_patent_app_number] => 10838830 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/838830
Use of non-lithographic shrink techniques for fabrication/making of imprints masks May 3, 2004 Issued
Array ( [id] => 498706 [patent_doc_number] => 07216318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-08 [patent_title] => 'Method and system for false path analysis' [patent_app_type] => utility [patent_app_number] => 10/836700 [patent_app_country] => US [patent_app_date] => 2004-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5547 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/216/07216318.pdf [firstpage_image] =>[orig_patent_app_number] => 10836700 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/836700
Method and system for false path analysis Apr 28, 2004 Issued
Array ( [id] => 726664 [patent_doc_number] => 07051305 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-23 [patent_title] => 'Delay estimation using edge specific miller capacitances' [patent_app_type] => utility [patent_app_number] => 10/832760 [patent_app_country] => US [patent_app_date] => 2004-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2581 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/051/07051305.pdf [firstpage_image] =>[orig_patent_app_number] => 10832760 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/832760
Delay estimation using edge specific miller capacitances Apr 26, 2004 Issued
Array ( [id] => 609713 [patent_doc_number] => 07155693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-26 [patent_title] => 'Floorplanning a hierarchical physical design to improve placement and routing' [patent_app_type] => utility [patent_app_number] => 10/831700 [patent_app_country] => US [patent_app_date] => 2004-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5725 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/155/07155693.pdf [firstpage_image] =>[orig_patent_app_number] => 10831700 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/831700
Floorplanning a hierarchical physical design to improve placement and routing Apr 22, 2004 Issued
Array ( [id] => 749852 [patent_doc_number] => 07032196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/828230 [patent_app_country] => US [patent_app_date] => 2004-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 35 [patent_no_of_words] => 13005 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032196.pdf [firstpage_image] =>[orig_patent_app_number] => 10828230 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/828230
Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device Apr 20, 2004 Issued
Array ( [id] => 6968404 [patent_doc_number] => 20050235240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Method for reducing layers revision in engineering change order' [patent_app_type] => utility [patent_app_number] => 10/826560 [patent_app_country] => US [patent_app_date] => 2004-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2382 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20050235240.pdf [firstpage_image] =>[orig_patent_app_number] => 10826560 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/826560
Method for reducing layers revision in engineering change order Apr 15, 2004 Issued
Array ( [id] => 6954035 [patent_doc_number] => 20050229130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements' [patent_app_type] => utility [patent_app_number] => 10/820260 [patent_app_country] => US [patent_app_date] => 2004-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3633 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20050229130.pdf [firstpage_image] =>[orig_patent_app_number] => 10820260 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/820260
Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements Apr 6, 2004 Abandoned
Array ( [id] => 6974080 [patent_doc_number] => 20050039156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-17 [patent_title] => 'Design method for essentially digital systems and components thereof and essentially digital systems made in accordance with the method' [patent_app_type] => utility [patent_app_number] => 10/817310 [patent_app_country] => US [patent_app_date] => 2004-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 21898 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20050039156.pdf [firstpage_image] =>[orig_patent_app_number] => 10817310 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/817310
Design method for essentially digital systems and components thereof and essentially digital systems made in accordance with the method Apr 1, 2004 Issued
Array ( [id] => 616001 [patent_doc_number] => 07149993 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-12 [patent_title] => 'Method, system, and apparatus for incremental design in programmable logic devices using floorplanning' [patent_app_type] => utility [patent_app_number] => 10/812550 [patent_app_country] => US [patent_app_date] => 2004-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3208 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149993.pdf [firstpage_image] =>[orig_patent_app_number] => 10812550 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/812550
Method, system, and apparatus for incremental design in programmable logic devices using floorplanning Mar 28, 2004 Issued
Array ( [id] => 6962782 [patent_doc_number] => 20050216870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'IC DESIGN DENSITY CHECKING METHOD, SYSTEM AND PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 10/708820 [patent_app_country] => US [patent_app_date] => 2004-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2512 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216870.pdf [firstpage_image] =>[orig_patent_app_number] => 10708820 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/708820
IC design density checking method, system and program product Mar 25, 2004 Issued
Array ( [id] => 7672014 [patent_doc_number] => 20040181765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Layout and wiring system and recording medium recording the wiring method' [patent_app_type] => new [patent_app_number] => 10/808530 [patent_app_country] => US [patent_app_date] => 2004-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9091 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20040181765.pdf [firstpage_image] =>[orig_patent_app_number] => 10808530 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/808530
Layout and wiring system and recording medium recording the wiring method Mar 24, 2004 Issued
Array ( [id] => 7113109 [patent_doc_number] => 20050210426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'System and method to prioritize and selectively apply configuration information for VLSI circuit analysis tools' [patent_app_type] => utility [patent_app_number] => 10/803610 [patent_app_country] => US [patent_app_date] => 2004-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5635 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20050210426.pdf [firstpage_image] =>[orig_patent_app_number] => 10803610 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/803610
System and method to prioritize and selectively apply configuration information for VLSI circuit analysis tools Mar 17, 2004 Abandoned
Array ( [id] => 6954049 [patent_doc_number] => 20050229144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Yield profile manipulator' [patent_app_type] => utility [patent_app_number] => 10/801310 [patent_app_country] => US [patent_app_date] => 2004-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3463 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20050229144.pdf [firstpage_image] =>[orig_patent_app_number] => 10801310 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/801310
Yield profile manipulator Mar 15, 2004 Issued
Array ( [id] => 7419147 [patent_doc_number] => 20040177334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Method and apparatus for automatically generating a phase lock loop (PLL)' [patent_app_type] => new [patent_app_number] => 10/796245 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12790 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20040177334.pdf [firstpage_image] =>[orig_patent_app_number] => 10796245 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796245
Method and apparatus for automatically generating a phase lock loop (PLL) Mar 7, 2004 Abandoned
Array ( [id] => 7076135 [patent_doc_number] => 20050149310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Method for integrating ethernet switch system and RTL design environment' [patent_app_type] => utility [patent_app_number] => 10/793780 [patent_app_country] => US [patent_app_date] => 2004-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1472 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20050149310.pdf [firstpage_image] =>[orig_patent_app_number] => 10793780 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/793780
Method for integrating ethernet switch system and RTL design environment Mar 7, 2004 Abandoned
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