Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 794471 [patent_doc_number] => 06983436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Method for correcting crosstalk' [patent_app_type] => utility [patent_app_number] => 10/690651 [patent_app_country] => US [patent_app_date] => 2003-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 9281 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/983/06983436.pdf [firstpage_image] =>[orig_patent_app_number] => 10690651 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/690651
Method for correcting crosstalk Oct 22, 2003 Issued
Array ( [id] => 960196 [patent_doc_number] => 06954918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Integrated circuit cells' [patent_app_type] => utility [patent_app_number] => 10/691410 [patent_app_country] => US [patent_app_date] => 2003-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4891 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954918.pdf [firstpage_image] =>[orig_patent_app_number] => 10691410 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/691410
Integrated circuit cells Oct 21, 2003 Issued
Array ( [id] => 877919 [patent_doc_number] => 07363600 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-22 [patent_title] => 'Method of simulating bidirectional signals in a modeling system' [patent_app_type] => utility [patent_app_number] => 10/691343 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6749 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/363/07363600.pdf [firstpage_image] =>[orig_patent_app_number] => 10691343 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/691343
Method of simulating bidirectional signals in a modeling system Oct 20, 2003 Issued
Array ( [id] => 7167483 [patent_doc_number] => 20050086624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Process and apparatus for fast assignment of objects to a rectangle' [patent_app_type] => utility [patent_app_number] => 10/688460 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2221 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20050086624.pdf [firstpage_image] =>[orig_patent_app_number] => 10688460 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/688460
Process and apparatus for fast assignment of objects to a rectangle Oct 16, 2003 Issued
Array ( [id] => 7167523 [patent_doc_number] => 20050086629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Method of defining forbidden pitches for a lithography exposure tool' [patent_app_type] => utility [patent_app_number] => 10/688500 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4902 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0086/20050086629.pdf [firstpage_image] =>[orig_patent_app_number] => 10688500 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/688500
Method of defining forbidden pitches for a lithography exposure tool Oct 16, 2003 Issued
Array ( [id] => 7392355 [patent_doc_number] => 20040083439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects' [patent_app_type] => new [patent_app_number] => 10/688559 [patent_app_country] => US [patent_app_date] => 2003-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 17815 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20040083439.pdf [firstpage_image] =>[orig_patent_app_number] => 10688559 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/688559
Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects Oct 15, 2003 Issued
Array ( [id] => 7341817 [patent_doc_number] => 20040133867 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Automatic design system for wiring on LSI, and method for wiring on LSI' [patent_app_type] => new [patent_app_number] => 10/681640 [patent_app_country] => US [patent_app_date] => 2003-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8391 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20040133867.pdf [firstpage_image] =>[orig_patent_app_number] => 10681640 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/681640
Automatic design system for wiring on LSI Oct 7, 2003 Issued
Array ( [id] => 691258 [patent_doc_number] => 07080335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-18 [patent_title] => 'Methods for modeling latch transparency' [patent_app_type] => utility [patent_app_number] => 10/672500 [patent_app_country] => US [patent_app_date] => 2003-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5411 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080335.pdf [firstpage_image] =>[orig_patent_app_number] => 10672500 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/672500
Methods for modeling latch transparency Sep 25, 2003 Issued
Array ( [id] => 7598012 [patent_doc_number] => 07584441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-01 [patent_title] => 'Method for generating optimized constraint systems for retimable digital designs' [patent_app_type] => utility [patent_app_number] => 10/665880 [patent_app_country] => US [patent_app_date] => 2003-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 4383 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/584/07584441.pdf [firstpage_image] =>[orig_patent_app_number] => 10665880 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/665880
Method for generating optimized constraint systems for retimable digital designs Sep 18, 2003 Issued
Array ( [id] => 7129519 [patent_doc_number] => 20050060674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'System and method for calculating effective capacitance for timing analysis' [patent_app_type] => utility [patent_app_number] => 10/662540 [patent_app_country] => US [patent_app_date] => 2003-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6200 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20050060674.pdf [firstpage_image] =>[orig_patent_app_number] => 10662540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/662540
System and method for calculating effective capacitance for timing analysis Sep 14, 2003 Issued
Array ( [id] => 676490 [patent_doc_number] => 07093222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Power supply wiring method for semiconductor integrated circuit and semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/653940 [patent_app_country] => US [patent_app_date] => 2003-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 6828 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/093/07093222.pdf [firstpage_image] =>[orig_patent_app_number] => 10653940 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653940
Power supply wiring method for semiconductor integrated circuit and semiconductor integrated circuit Sep 3, 2003 Issued
Array ( [id] => 713959 [patent_doc_number] => 07062744 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Emulation solution for programmable instruction DSP' [patent_app_type] => utility [patent_app_number] => 10/655060 [patent_app_country] => US [patent_app_date] => 2003-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 9574 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/062/07062744.pdf [firstpage_image] =>[orig_patent_app_number] => 10655060 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/655060
Emulation solution for programmable instruction DSP Sep 2, 2003 Issued
Array ( [id] => 7607996 [patent_doc_number] => 07000204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'Power estimation based on power characterizations' [patent_app_type] => utility [patent_app_number] => 10/653650 [patent_app_country] => US [patent_app_date] => 2003-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5909 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000204.pdf [firstpage_image] =>[orig_patent_app_number] => 10653650 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/653650
Power estimation based on power characterizations Sep 1, 2003 Issued
Array ( [id] => 7084463 [patent_doc_number] => 20050049843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Computerized extension apparatus and methods' [patent_app_type] => utility [patent_app_number] => 10/651560 [patent_app_country] => US [patent_app_date] => 2003-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 18606 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20050049843.pdf [firstpage_image] =>[orig_patent_app_number] => 10651560 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651560
Computerized extension apparatus and methods Aug 28, 2003 Abandoned
Array ( [id] => 7084461 [patent_doc_number] => 20050049841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Simulation management system' [patent_app_type] => utility [patent_app_number] => 10/651150 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9284 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20050049841.pdf [firstpage_image] =>[orig_patent_app_number] => 10651150 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651150
Simulation management system Aug 27, 2003 Issued
Array ( [id] => 705965 [patent_doc_number] => 07069528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'System and method for reducing timing violations due to crosstalk in an integrated circuit design' [patent_app_type] => utility [patent_app_number] => 10/650010 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5562 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/069/07069528.pdf [firstpage_image] =>[orig_patent_app_number] => 10650010 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/650010
System and method for reducing timing violations due to crosstalk in an integrated circuit design Aug 26, 2003 Issued
Array ( [id] => 7605593 [patent_doc_number] => 07100130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Device for the emulation of designs for integrated circuits' [patent_app_type] => utility [patent_app_number] => 10/649230 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4955 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/100/07100130.pdf [firstpage_image] =>[orig_patent_app_number] => 10649230 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649230
Device for the emulation of designs for integrated circuits Aug 25, 2003 Issued
Array ( [id] => 7413674 [patent_doc_number] => 20040025139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Mask pattern and method for forming resist pattern using mask pattern thereof' [patent_app_type] => new [patent_app_number] => 10/632850 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5929 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20040025139.pdf [firstpage_image] =>[orig_patent_app_number] => 10632850 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/632850
Mask pattern and method for forming resist pattern using mask pattern thereof Aug 3, 2003 Issued
Array ( [id] => 685077 [patent_doc_number] => 07086030 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-01 [patent_title] => 'Incremental netlisting' [patent_app_type] => utility [patent_app_number] => 10/633830 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3150 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/086/07086030.pdf [firstpage_image] =>[orig_patent_app_number] => 10633830 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633830
Incremental netlisting Aug 3, 2003 Issued
Array ( [id] => 7387957 [patent_doc_number] => 20040021490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Method and apparatus for timing management in a converted design' [patent_app_type] => new [patent_app_number] => 10/631410 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6804 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20040021490.pdf [firstpage_image] =>[orig_patent_app_number] => 10631410 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631410
Method and apparatus for timing management in a converted design Jul 29, 2003 Abandoned
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