Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 294256 [patent_doc_number] => 07546556 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-06-09 [patent_title] => 'Virtual shape based parameterized cell' [patent_app_type] => utility [patent_app_number] => 10/426470 [patent_app_country] => US [patent_app_date] => 2003-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 4560 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/546/07546556.pdf [firstpage_image] =>[orig_patent_app_number] => 10426470 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426470
Virtual shape based parameterized cell Apr 28, 2003 Issued
Array ( [id] => 786218 [patent_doc_number] => 06993729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Method, system and program product for specifying a dial group for a digital system described by a hardware description language (HDL) model' [patent_app_type] => utility [patent_app_number] => 10/425070 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 46 [patent_no_of_words] => 39069 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/993/06993729.pdf [firstpage_image] =>[orig_patent_app_number] => 10425070 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425070
Method, system and program product for specifying a dial group for a digital system described by a hardware description language (HDL) model Apr 27, 2003 Issued
Array ( [id] => 7298983 [patent_doc_number] => 20040215432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Method, system and program product for specifying a configuration for multiple signal or dial instances in a digital system' [patent_app_type] => new [patent_app_number] => 10/425051 [patent_app_country] => US [patent_app_date] => 2003-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 39335 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20040215432.pdf [firstpage_image] =>[orig_patent_app_number] => 10425051 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/425051
Method, system and program product for specifying a configuration for multiple signal or dial instances in a digital system Apr 27, 2003 Issued
Array ( [id] => 7673696 [patent_doc_number] => 20040128422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Storage device implementing multiple interfaces using a single ASIC' [patent_app_type] => new [patent_app_number] => 10/421572 [patent_app_country] => US [patent_app_date] => 2003-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4520 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128422.pdf [firstpage_image] =>[orig_patent_app_number] => 10421572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/421572
Storage device implementing multiple interfaces using a single ASIC Apr 21, 2003 Abandoned
Array ( [id] => 6648408 [patent_doc_number] => 20030212963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Method and apparatus for jump control in a pipelined processor' [patent_app_type] => new [patent_app_number] => 10/420299 [patent_app_country] => US [patent_app_date] => 2003-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7720 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20030212963.pdf [firstpage_image] =>[orig_patent_app_number] => 10420299 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/420299
Method and apparatus for jump control in a pipelined processor Apr 20, 2003 Issued
Array ( [id] => 7673491 [patent_doc_number] => 20040128627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Methods implementing multiple interfaces for a storage device using a single ASIC' [patent_app_type] => new [patent_app_number] => 10/419540 [patent_app_country] => US [patent_app_date] => 2003-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4516 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128627.pdf [firstpage_image] =>[orig_patent_app_number] => 10419540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/419540
Methods implementing multiple interfaces for a storage device using a single ASIC Apr 20, 2003 Abandoned
Array ( [id] => 6794772 [patent_doc_number] => 20030173645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Delay circuit, testing apparatus, and capacitor' [patent_app_type] => new [patent_app_number] => 10/413344 [patent_app_country] => US [patent_app_date] => 2003-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3519 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20030173645.pdf [firstpage_image] =>[orig_patent_app_number] => 10413344 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/413344
Delay circuit, testing apparatus, and capacitor Apr 13, 2003 Issued
Array ( [id] => 962338 [patent_doc_number] => 06952810 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-04 [patent_title] => 'Coding speed and correctness of hardware description language (HDL) descriptions of hardware' [patent_app_type] => utility [patent_app_number] => 10/413280 [patent_app_country] => US [patent_app_date] => 2003-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5494 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/952/06952810.pdf [firstpage_image] =>[orig_patent_app_number] => 10413280 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/413280
Coding speed and correctness of hardware description language (HDL) descriptions of hardware Apr 13, 2003 Issued
Array ( [id] => 7611263 [patent_doc_number] => 06904579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Reducing time to measure constraint parameters of components in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/403080 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4603 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904579.pdf [firstpage_image] =>[orig_patent_app_number] => 10403080 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/403080
Reducing time to measure constraint parameters of components in an integrated circuit Mar 31, 2003 Issued
Array ( [id] => 7445642 [patent_doc_number] => 20040196081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Minimization of clock skew and clock phase delay in integrated circuits' [patent_app_type] => new [patent_app_number] => 10/405926 [patent_app_country] => US [patent_app_date] => 2003-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6455 [patent_no_of_claims] => 79 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20040196081.pdf [firstpage_image] =>[orig_patent_app_number] => 10405926 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/405926
Minimization of clock skew and clock phase delay in integrated circuits Mar 31, 2003 Abandoned
Array ( [id] => 7607989 [patent_doc_number] => 07000211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-14 [patent_title] => 'System and method for efficiently mapping heterogeneous objects onto an array of heterogeneous programmable logic resources' [patent_app_type] => utility [patent_app_number] => 10/404680 [patent_app_country] => US [patent_app_date] => 2003-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5631 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/000/07000211.pdf [firstpage_image] =>[orig_patent_app_number] => 10404680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/404680
System and method for efficiently mapping heterogeneous objects onto an array of heterogeneous programmable logic resources Mar 30, 2003 Issued
Array ( [id] => 7271515 [patent_doc_number] => 20040060033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Mask data processor' [patent_app_type] => new [patent_app_number] => 10/397520 [patent_app_country] => US [patent_app_date] => 2003-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12450 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0060/20040060033.pdf [firstpage_image] =>[orig_patent_app_number] => 10397520 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/397520
Mask data processor Mar 26, 2003 Issued
Array ( [id] => 1059107 [patent_doc_number] => 06857114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Clustering for data compression' [patent_app_type] => utility [patent_app_number] => 10/397085 [patent_app_country] => US [patent_app_date] => 2003-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7825 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/857/06857114.pdf [firstpage_image] =>[orig_patent_app_number] => 10397085 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/397085
Clustering for data compression Mar 24, 2003 Issued
Array ( [id] => 6728161 [patent_doc_number] => 20030184351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Timing signal occurrence circuit' [patent_app_type] => new [patent_app_number] => 10/390926 [patent_app_country] => US [patent_app_date] => 2003-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3391 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20030184351.pdf [firstpage_image] =>[orig_patent_app_number] => 10390926 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/390926
Timing signal occurrence circuit Mar 18, 2003 Abandoned
Array ( [id] => 7138802 [patent_doc_number] => 20040044967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Semiconductor intellectual property transmission system' [patent_app_type] => new [patent_app_number] => 10/387490 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4878 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20040044967.pdf [firstpage_image] =>[orig_patent_app_number] => 10387490 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/387490
Semiconductor intellectual property transmission system Mar 13, 2003 Abandoned
Array ( [id] => 7672011 [patent_doc_number] => 20040181768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Model pattern simulation of semiconductor wafer processing steps' [patent_app_type] => new [patent_app_number] => 10/388120 [patent_app_country] => US [patent_app_date] => 2003-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8606 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20040181768.pdf [firstpage_image] =>[orig_patent_app_number] => 10388120 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/388120
Model pattern simulation of semiconductor wafer processing steps Mar 11, 2003 Abandoned
Array ( [id] => 774427 [patent_doc_number] => 07007250 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-28 [patent_title] => 'Application-specific methods useful for testing look up tables in programmable logic devices' [patent_app_type] => utility [patent_app_number] => 10/388000 [patent_app_country] => US [patent_app_date] => 2003-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6406 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/007/07007250.pdf [firstpage_image] =>[orig_patent_app_number] => 10388000 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/388000
Application-specific methods useful for testing look up tables in programmable logic devices Mar 11, 2003 Issued
Array ( [id] => 7419142 [patent_doc_number] => 20040177333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Method and apparatus for a configurable metal register' [patent_app_type] => new [patent_app_number] => 10/383120 [patent_app_country] => US [patent_app_date] => 2003-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2916 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20040177333.pdf [firstpage_image] =>[orig_patent_app_number] => 10383120 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/383120
Method and apparatus for a configurable metal register Mar 5, 2003 Issued
Array ( [id] => 707086 [patent_doc_number] => 07065725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Semiconductor manufacturing apparatus, management apparatus therefor, component management apparatus therefor, and semiconductor wafer storage vessel transport apparatus' [patent_app_type] => utility [patent_app_number] => 10/377770 [patent_app_country] => US [patent_app_date] => 2003-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 55 [patent_no_of_words] => 10678 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/065/07065725.pdf [firstpage_image] =>[orig_patent_app_number] => 10377770 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/377770
Semiconductor manufacturing apparatus, management apparatus therefor, component management apparatus therefor, and semiconductor wafer storage vessel transport apparatus Mar 3, 2003 Issued
Array ( [id] => 7474435 [patent_doc_number] => 20040054981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Method of manufacturing electronic device' [patent_app_type] => new [patent_app_number] => 10/360860 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9559 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20040054981.pdf [firstpage_image] =>[orig_patent_app_number] => 10360860 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/360860
Method of manufacturing electronic device Feb 9, 2003 Issued
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