Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 659663 [patent_doc_number] => 07111265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-19 [patent_title] => 'I/O pin placement for a programmable logic device' [patent_app_type] => utility [patent_app_number] => 10/353453 [patent_app_country] => US [patent_app_date] => 2003-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5458 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111265.pdf [firstpage_image] =>[orig_patent_app_number] => 10353453 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353453
I/O pin placement for a programmable logic device Jan 27, 2003 Issued
Array ( [id] => 7312866 [patent_doc_number] => 20040143803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Simulated voltage contrast image generator and comparator' [patent_app_type] => new [patent_app_number] => 10/349770 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4470 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20040143803.pdf [firstpage_image] =>[orig_patent_app_number] => 10349770 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/349770
Simulated voltage contrasted image generator and comparator Jan 21, 2003 Issued
Array ( [id] => 7312851 [patent_doc_number] => 20040143800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Method and apparatus for modeling dynamic systems' [patent_app_type] => new [patent_app_number] => 10/349540 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5664 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20040143800.pdf [firstpage_image] =>[orig_patent_app_number] => 10349540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/349540
Method and apparatus for modeling dynamic systems Jan 21, 2003 Issued
Array ( [id] => 7312848 [patent_doc_number] => 20040143797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => '7-Tracks standard cell library' [patent_app_type] => new [patent_app_number] => 10/346970 [patent_app_country] => US [patent_app_date] => 2003-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7025 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20040143797.pdf [firstpage_image] =>[orig_patent_app_number] => 10346970 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/346970
7-tracks standard cell library Jan 16, 2003 Issued
Array ( [id] => 163577 [patent_doc_number] => 07676781 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-09 [patent_title] => 'Method and mechanism for implementing a minimum spanning tree' [patent_app_type] => utility [patent_app_number] => 10/342640 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3818 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/676/07676781.pdf [firstpage_image] =>[orig_patent_app_number] => 10342640 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/342640
Method and mechanism for implementing a minimum spanning tree Jan 13, 2003 Issued
Array ( [id] => 7368219 [patent_doc_number] => 20040015793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Methodology for the optimization of testing and diagnosis of analog and mixed signal ICs and embedded cores' [patent_app_type] => new [patent_app_number] => 10/339060 [patent_app_country] => US [patent_app_date] => 2003-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5309 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015793.pdf [firstpage_image] =>[orig_patent_app_number] => 10339060 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339060
Methodology for the optimization of testing and diagnosis of analog and mixed signal ICs and embedded cores Jan 8, 2003 Issued
Array ( [id] => 7673477 [patent_doc_number] => 20040128641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Simplified process to design integrated circuits' [patent_app_type] => new [patent_app_number] => 10/335360 [patent_app_country] => US [patent_app_date] => 2002-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10252 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20040128641.pdf [firstpage_image] =>[orig_patent_app_number] => 10335360 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/335360
Simplified process to design integrated circuits Dec 30, 2002 Issued
Array ( [id] => 7474429 [patent_doc_number] => 20040054977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Delay model circuit for use in delay locked loop' [patent_app_type] => new [patent_app_number] => 10/329936 [patent_app_country] => US [patent_app_date] => 2002-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3732 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20040054977.pdf [firstpage_image] =>[orig_patent_app_number] => 10329936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329936
Delay model circuit for use in delay locked loop Dec 25, 2002 Issued
Array ( [id] => 7477282 [patent_doc_number] => 20040123252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Method and apparatus for providing feedback from a compactor to a router to facilitate layout of an integrated circuit' [patent_app_type] => new [patent_app_number] => 10/329010 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2099 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20040123252.pdf [firstpage_image] =>[orig_patent_app_number] => 10329010 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/329010
Method and apparatus for providing feedback from a compactor to a router to facilitate layout of an integrated circuit Dec 22, 2002 Issued
Array ( [id] => 7459497 [patent_doc_number] => 20040119496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Implementation of multiple flip flops as a standard cell using novel clock generation scheme' [patent_app_type] => new [patent_app_number] => 10/328820 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5366 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20040119496.pdf [firstpage_image] =>[orig_patent_app_number] => 10328820 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/328820
Implementation of multiple flip flops as a standard cell using novel clock generation scheme Dec 22, 2002 Abandoned
Array ( [id] => 680408 [patent_doc_number] => 07089509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Controlling the propagation of a control signal by means of variable I/O delay compensation using a programmable delay circuit and detection sequence' [patent_app_type] => utility [patent_app_number] => 10/328565 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4770 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/089/07089509.pdf [firstpage_image] =>[orig_patent_app_number] => 10328565 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/328565
Controlling the propagation of a control signal by means of variable I/O delay compensation using a programmable delay circuit and detection sequence Dec 22, 2002 Issued
Array ( [id] => 7215995 [patent_doc_number] => 20040088659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Semiconductor device having scan flip-flop and design method therefor' [patent_app_type] => new [patent_app_number] => 10/325740 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10098 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20040088659.pdf [firstpage_image] =>[orig_patent_app_number] => 10325740 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/325740
Semiconductor device having scan flip-flop and design method therefor Dec 22, 2002 Abandoned
Array ( [id] => 6793496 [patent_doc_number] => 20030088840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Method of designing semiconductor integrated circuit device, method of analyzing power consumption of circuit and apparatus for analyzing power consumption' [patent_app_type] => new [patent_app_number] => 10/326152 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 19014 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20030088840.pdf [firstpage_image] =>[orig_patent_app_number] => 10326152 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/326152
Method of designing semiconductor integrated circuit device, method of analyzing power consumption of circuit and apparatus for analyzing power consumption Dec 22, 2002 Abandoned
Array ( [id] => 953483 [patent_doc_number] => 06961917 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'Method for activating fuse units in electronic circuit device' [patent_app_type] => utility [patent_app_number] => 10/325100 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3591 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/961/06961917.pdf [firstpage_image] =>[orig_patent_app_number] => 10325100 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/325100
Method for activating fuse units in electronic circuit device Dec 19, 2002 Issued
Array ( [id] => 922260 [patent_doc_number] => 07325206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Electronic design for integrated circuits based process related variations' [patent_app_type] => utility [patent_app_number] => 10/321290 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 77 [patent_figures_cnt] => 96 [patent_no_of_words] => 25596 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/325/07325206.pdf [firstpage_image] =>[orig_patent_app_number] => 10321290 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/321290
Electronic design for integrated circuits based process related variations Dec 16, 2002 Issued
Array ( [id] => 749844 [patent_doc_number] => 07032193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Differentially mis-aligned contacts in flash arrays to calibrate failure modes' [patent_app_type] => utility [patent_app_number] => 10/320910 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1941 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032193.pdf [firstpage_image] =>[orig_patent_app_number] => 10320910 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/320910
Differentially mis-aligned contacts in flash arrays to calibrate failure modes Dec 16, 2002 Issued
Array ( [id] => 958317 [patent_doc_number] => 06957399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'Controlling the propagation of a digital signal by means of variable I/O delay compensation using delay-tracking' [patent_app_type] => utility [patent_app_number] => 10/317740 [patent_app_country] => US [patent_app_date] => 2002-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4462 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957399.pdf [firstpage_image] =>[orig_patent_app_number] => 10317740 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/317740
Controlling the propagation of a digital signal by means of variable I/O delay compensation using delay-tracking Dec 11, 2002 Issued
Array ( [id] => 6645498 [patent_doc_number] => 20030104288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Reference image generation from subject image for photolithography mask analysis' [patent_app_type] => new [patent_app_number] => 10/316280 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7188 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20030104288.pdf [firstpage_image] =>[orig_patent_app_number] => 10316280 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/316280
Reference image generation from subject image for photolithography mask analysis Dec 9, 2002 Issued
Array ( [id] => 7092095 [patent_doc_number] => 20050010883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Timing circuit cad' [patent_app_type] => utility [patent_app_number] => 10/497730 [patent_app_country] => US [patent_app_date] => 2002-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13155 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20050010883.pdf [firstpage_image] =>[orig_patent_app_number] => 10497730 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/497730
Timing circuit cad Dec 5, 2002 Issued
Array ( [id] => 1055893 [patent_doc_number] => 06859918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Alleviating line end shortening by extending phase shifters' [patent_app_type] => utility [patent_app_number] => 10/313325 [patent_app_country] => US [patent_app_date] => 2002-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2480 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859918.pdf [firstpage_image] =>[orig_patent_app_number] => 10313325 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/313325
Alleviating line end shortening by extending phase shifters Dec 5, 2002 Issued
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