Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1037280 [patent_doc_number] => 06877150 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-05 [patent_title] => 'Method of transforming software language constructs to functional hardware equivalents' [patent_app_type] => utility [patent_app_number] => 10/310520 [patent_app_country] => US [patent_app_date] => 2002-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8806 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/877/06877150.pdf [firstpage_image] =>[orig_patent_app_number] => 10310520 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/310520
Method of transforming software language constructs to functional hardware equivalents Dec 3, 2002 Issued
Array ( [id] => 7470127 [patent_doc_number] => 20040096752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Phase-width balanced alternating phase shift mask design' [patent_app_type] => new [patent_app_number] => 10/300240 [patent_app_country] => US [patent_app_date] => 2002-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20040096752.pdf [firstpage_image] =>[orig_patent_app_number] => 10300240 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300240
Phase-width balanced alternating phase shift mask design Nov 19, 2002 Issued
Array ( [id] => 6871725 [patent_doc_number] => 20030084415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'System and method for evaluation of electric characteristics of printed-circuit boards' [patent_app_type] => new [patent_app_number] => 10/291539 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9740 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20030084415.pdf [firstpage_image] =>[orig_patent_app_number] => 10291539 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291539
System and method for evaluation of electric characteristics of printed-circuit boards Nov 11, 2002 Issued
Array ( [id] => 6857833 [patent_doc_number] => 20030131334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Synthesis strategies based on the appropriate use of inductance effects' [patent_app_type] => new [patent_app_number] => 10/293900 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11150 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20030131334.pdf [firstpage_image] =>[orig_patent_app_number] => 10293900 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/293900
Synthesis strategies based on the appropriate use of inductance effects Nov 11, 2002 Issued
Array ( [id] => 774482 [patent_doc_number] => 07007262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-28 [patent_title] => 'High level synthesis method and apparatus' [patent_app_type] => utility [patent_app_number] => 10/291790 [patent_app_country] => US [patent_app_date] => 2002-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3814 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/007/07007262.pdf [firstpage_image] =>[orig_patent_app_number] => 10291790 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/291790
High level synthesis method and apparatus Nov 11, 2002 Issued
Array ( [id] => 691246 [patent_doc_number] => 07080329 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-07-18 [patent_title] => 'Method and apparatus for identifying optimized via locations' [patent_app_type] => utility [patent_app_number] => 10/288870 [patent_app_country] => US [patent_app_date] => 2002-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 98 [patent_no_of_words] => 30968 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/080/07080329.pdf [firstpage_image] =>[orig_patent_app_number] => 10288870 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/288870
Method and apparatus for identifying optimized via locations Nov 5, 2002 Issued
Array ( [id] => 7195512 [patent_doc_number] => 20040085823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Configurable amplifier array incorporating programmable EHF transmission lines' [patent_app_type] => new [patent_app_number] => 10/285150 [patent_app_country] => US [patent_app_date] => 2002-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5704 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20040085823.pdf [firstpage_image] =>[orig_patent_app_number] => 10285150 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/285150
Configurable amplifier array incorporating programmable EHF transmission lines Oct 30, 2002 Issued
Array ( [id] => 6793505 [patent_doc_number] => 20030088849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Semiconductor integrated circuit device and method for designing the same' [patent_app_type] => new [patent_app_number] => 10/281300 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 21034 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20030088849.pdf [firstpage_image] =>[orig_patent_app_number] => 10281300 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/281300
Semiconductor integrated circuit device and method for designing the same Oct 27, 2002 Issued
Array ( [id] => 6810536 [patent_doc_number] => 20030200475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-23 [patent_title] => 'Universal serial bus circuit and data structure' [patent_app_type] => new [patent_app_number] => 10/281248 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7850 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20030200475.pdf [firstpage_image] =>[orig_patent_app_number] => 10281248 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/281248
Universal serial bus circuit and data structure Oct 27, 2002 Issued
Array ( [id] => 740044 [patent_doc_number] => 07039887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Method and apparatus for enhancing the performance of event driven dynamic simulation of digital circuits based on netlist partitioning techniques' [patent_app_type] => utility [patent_app_number] => 10/272540 [patent_app_country] => US [patent_app_date] => 2002-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3586 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/039/07039887.pdf [firstpage_image] =>[orig_patent_app_number] => 10272540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/272540
Method and apparatus for enhancing the performance of event driven dynamic simulation of digital circuits based on netlist partitioning techniques Oct 14, 2002 Issued
Array ( [id] => 1179606 [patent_doc_number] => 06757879 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Signal routing in programmable logic devices' [patent_app_type] => B1 [patent_app_number] => 10/268878 [patent_app_country] => US [patent_app_date] => 2002-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3070 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757879.pdf [firstpage_image] =>[orig_patent_app_number] => 10268878 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/268878
Signal routing in programmable logic devices Oct 8, 2002 Issued
Array ( [id] => 1027790 [patent_doc_number] => 06886141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-26 [patent_title] => 'Method and system for reducing congestion in computer networks' [patent_app_type] => utility [patent_app_number] => 10/266360 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2081 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/886/06886141.pdf [firstpage_image] =>[orig_patent_app_number] => 10266360 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/266360
Method and system for reducing congestion in computer networks Oct 6, 2002 Issued
Array ( [id] => 1112244 [patent_doc_number] => 06810508 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Method for automatically-remapping an HDL netlist to provide compatibility with pre-synthesis behavioral test benches' [patent_app_type] => B1 [patent_app_number] => 10/266230 [patent_app_country] => US [patent_app_date] => 2002-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4361 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/810/06810508.pdf [firstpage_image] =>[orig_patent_app_number] => 10266230 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/266230
Method for automatically-remapping an HDL netlist to provide compatibility with pre-synthesis behavioral test benches Oct 6, 2002 Issued
Array ( [id] => 1100530 [patent_doc_number] => 06823501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method of generating the padring layout design using automation' [patent_app_type] => B1 [patent_app_number] => 10/264680 [patent_app_country] => US [patent_app_date] => 2002-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 11640 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/823/06823501.pdf [firstpage_image] =>[orig_patent_app_number] => 10264680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/264680
Method of generating the padring layout design using automation Oct 2, 2002 Issued
Array ( [id] => 6763206 [patent_doc_number] => 20030126568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Duty analysis system for a semiconductor integrated circuit and duty analysis method of the same' [patent_app_type] => new [patent_app_number] => 10/259500 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3198 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20030126568.pdf [firstpage_image] =>[orig_patent_app_number] => 10259500 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/259500
Duty analysis system for a semiconductor integrated circuit and duty analysis method of the same Sep 29, 2002 Issued
Array ( [id] => 6675970 [patent_doc_number] => 20030061573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Method and program for supporting register-transfer-level design of semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 10/255530 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8004 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061573.pdf [firstpage_image] =>[orig_patent_app_number] => 10255530 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/255530
Method and program for supporting register-transfer-level design of semiconductor integrated circuit Sep 25, 2002 Issued
Array ( [id] => 1170481 [patent_doc_number] => 06763509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'Method and apparatus for allocating decoupling capacitor cells' [patent_app_type] => B2 [patent_app_number] => 10/256580 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4063 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763509.pdf [firstpage_image] =>[orig_patent_app_number] => 10256580 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/256580
Method and apparatus for allocating decoupling capacitor cells Sep 25, 2002 Issued
Array ( [id] => 7628122 [patent_doc_number] => 06820240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Voltage island chip implementation' [patent_app_type] => B2 [patent_app_number] => 10/065201 [patent_app_country] => US [patent_app_date] => 2002-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 7105 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/820/06820240.pdf [firstpage_image] =>[orig_patent_app_number] => 10065201 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/065201
Voltage island chip implementation Sep 24, 2002 Issued
Array ( [id] => 707081 [patent_doc_number] => 07065723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Defect tracking by utilizing real-time counters in network computing environments' [patent_app_type] => utility [patent_app_number] => 10/255800 [patent_app_country] => US [patent_app_date] => 2002-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3505 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/065/07065723.pdf [firstpage_image] =>[orig_patent_app_number] => 10255800 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/255800
Defect tracking by utilizing real-time counters in network computing environments Sep 24, 2002 Issued
Array ( [id] => 1112257 [patent_doc_number] => 06810515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-26 [patent_title] => 'Process of restructuring logics in ICs for setup and hold time optimization' [patent_app_type] => B2 [patent_app_number] => 10/254380 [patent_app_country] => US [patent_app_date] => 2002-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5231 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/810/06810515.pdf [firstpage_image] =>[orig_patent_app_number] => 10254380 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254380
Process of restructuring logics in ICs for setup and hold time optimization Sep 24, 2002 Issued
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