
Paul Dinh
Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2816, 2825 |
| Total Applications | 2030 |
| Issued Applications | 1783 |
| Pending Applications | 89 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7623744
[patent_doc_number] => 06725433
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[patent_kind] => B1
[patent_issue_date] => 2004-04-20
[patent_title] => 'Method for assessing the reliability of interconnects'
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Array
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[patent_issue_date] => 2004-11-23
[patent_title] => 'Method for designing application specific integrated circuit structure'
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Array
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Array
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[patent_title] => 'Method and apparatus for waiving noise violations'
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Array
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Array
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Array
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[patent_title] => 'Method and apparatus for improving PIP coverage in programmable logic devices'
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Array
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Array
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Array
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