Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7623744 [patent_doc_number] => 06725433 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-20 [patent_title] => 'Method for assessing the reliability of interconnects' [patent_app_type] => B1 [patent_app_number] => 10/252680 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/725/06725433.pdf [firstpage_image] =>[orig_patent_app_number] => 10252680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/252680
Method for assessing the reliability of interconnects Sep 23, 2002 Issued
Array ( [id] => 1100526 [patent_doc_number] => 06823499 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Method for designing application specific integrated circuit structure' [patent_app_type] => B1 [patent_app_number] => 10/245140 [patent_app_country] => US [patent_app_date] => 2002-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3479 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/823/06823499.pdf [firstpage_image] =>[orig_patent_app_number] => 10245140 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/245140
Method for designing application specific integrated circuit structure Sep 15, 2002 Issued
Array ( [id] => 1017402 [patent_doc_number] => 06895571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Nanometer scale devices' [patent_app_type] => utility [patent_app_number] => 10/242405 [patent_app_country] => US [patent_app_date] => 2002-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4253 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/895/06895571.pdf [firstpage_image] =>[orig_patent_app_number] => 10242405 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/242405
Nanometer scale devices Sep 12, 2002 Issued
Array ( [id] => 7361246 [patent_doc_number] => 20040049745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Method and apparatus for waiving noise violations' [patent_app_type] => new [patent_app_number] => 10/236840 [patent_app_country] => US [patent_app_date] => 2002-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2649 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20040049745.pdf [firstpage_image] =>[orig_patent_app_number] => 10236840 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/236840
Method and apparatus for waiving noise violations Sep 5, 2002 Abandoned
Array ( [id] => 975621 [patent_doc_number] => 06938225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-30 [patent_title] => 'Scan design for double-edge-triggered flip-flops' [patent_app_type] => utility [patent_app_number] => 10/235118 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5120 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/938/06938225.pdf [firstpage_image] =>[orig_patent_app_number] => 10235118 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/235118
Scan design for double-edge-triggered flip-flops Sep 3, 2002 Issued
Array ( [id] => 6815089 [patent_doc_number] => 20030074639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Method for automatically correcting overlay alignment of a semiconductor wafer' [patent_app_type] => new [patent_app_number] => 10/233556 [patent_app_country] => US [patent_app_date] => 2002-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2974 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074639.pdf [firstpage_image] =>[orig_patent_app_number] => 10233556 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233556
Method for automatically correcting overlay alignment of a semiconductor wafer Sep 3, 2002 Issued
Array ( [id] => 1134573 [patent_doc_number] => 06792592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Considering mask writer properties during the optical proximity correction process' [patent_app_type] => B2 [patent_app_number] => 10/232130 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 3987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/792/06792592.pdf [firstpage_image] =>[orig_patent_app_number] => 10232130 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232130
Considering mask writer properties during the optical proximity correction process Aug 29, 2002 Issued
Array ( [id] => 1062354 [patent_doc_number] => 06854106 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Reticles and methods of forming and using the same' [patent_app_type] => utility [patent_app_number] => 10/230950 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4148 [patent_no_of_claims] => 89 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/854/06854106.pdf [firstpage_image] =>[orig_patent_app_number] => 10230950 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230950
Reticles and methods of forming and using the same Aug 28, 2002 Issued
Array ( [id] => 1197249 [patent_doc_number] => 06732349 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method and apparatus for improving PIP coverage in programmable logic devices' [patent_app_type] => B1 [patent_app_number] => 10/231900 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3053 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732349.pdf [firstpage_image] =>[orig_patent_app_number] => 10231900 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231900
Method and apparatus for improving PIP coverage in programmable logic devices Aug 28, 2002 Issued
Array ( [id] => 7621070 [patent_doc_number] => 06978432 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-20 [patent_title] => 'Method and apparatus for propagating a piecewise linear function to a point' [patent_app_type] => utility [patent_app_number] => 10/232795 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 55 [patent_no_of_words] => 28222 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/978/06978432.pdf [firstpage_image] =>[orig_patent_app_number] => 10232795 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232795
Method and apparatus for propagating a piecewise linear function to a point Aug 27, 2002 Issued
Array ( [id] => 7138841 [patent_doc_number] => 20040044980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Method and apparatus for designing a pattern on a semiconductor surface' [patent_app_type] => new [patent_app_number] => 10/229330 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7046 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20040044980.pdf [firstpage_image] =>[orig_patent_app_number] => 10229330 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229330
Method and apparatus for designing a pattern on a semiconductor surface Aug 26, 2002 Issued
Array ( [id] => 7138836 [patent_doc_number] => 20040044979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Constraint-based global router for routing high performance designs' [patent_app_type] => new [patent_app_number] => 10/228540 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13416 [patent_no_of_claims] => 87 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20040044979.pdf [firstpage_image] =>[orig_patent_app_number] => 10228540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/228540
Constraint-based global router for routing high performance designs Aug 26, 2002 Abandoned
Array ( [id] => 7603472 [patent_doc_number] => 07117468 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-03 [patent_title] => 'Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts' [patent_app_type] => utility [patent_app_number] => 10/229170 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 79 [patent_figures_cnt] => 156 [patent_no_of_words] => 65732 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117468.pdf [firstpage_image] =>[orig_patent_app_number] => 10229170 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229170
Layouts with routes with different spacings in different directions on the same layer, and method and apparatus for generating such layouts Aug 25, 2002 Issued
Array ( [id] => 1155860 [patent_doc_number] => 06779171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Field correction of overlay error' [patent_app_type] => B2 [patent_app_number] => 10/229360 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7149 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/779/06779171.pdf [firstpage_image] =>[orig_patent_app_number] => 10229360 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/229360
Field correction of overlay error Aug 25, 2002 Issued
Array ( [id] => 7316288 [patent_doc_number] => 20040034837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Numerically modeling inductive circuit elements' [patent_app_type] => new [patent_app_number] => 10/224170 [patent_app_country] => US [patent_app_date] => 2002-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6213 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20040034837.pdf [firstpage_image] =>[orig_patent_app_number] => 10224170 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224170
Numerically modeling inductive circuit elements Aug 18, 2002 Issued
Array ( [id] => 1150135 [patent_doc_number] => 06782520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'IC layout system having separate trial and detailed routing phases' [patent_app_type] => B1 [patent_app_number] => 10/217851 [patent_app_country] => US [patent_app_date] => 2002-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4173 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/782/06782520.pdf [firstpage_image] =>[orig_patent_app_number] => 10217851 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/217851
IC layout system having separate trial and detailed routing phases Aug 11, 2002 Issued
Array ( [id] => 1258710 [patent_doc_number] => 06671862 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'Method and apparatus for simplifying a circuit model' [patent_app_type] => B1 [patent_app_number] => 10/213960 [patent_app_country] => US [patent_app_date] => 2002-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671862.pdf [firstpage_image] =>[orig_patent_app_number] => 10213960 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/213960
Method and apparatus for simplifying a circuit model Aug 6, 2002 Issued
Array ( [id] => 6815087 [patent_doc_number] => 20030074637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Clock generation system for a prototyping apparatus' [patent_app_type] => new [patent_app_number] => 10/212120 [patent_app_country] => US [patent_app_date] => 2002-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8074 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074637.pdf [firstpage_image] =>[orig_patent_app_number] => 10212120 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212120
Clock generation system for a prototyping apparatus Aug 5, 2002 Issued
Array ( [id] => 7413590 [patent_doc_number] => 20040025126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'System and method for providing compliant mapping between chip bond locations and package bond locations for an integrated circuit' [patent_app_type] => new [patent_app_number] => 10/212360 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3718 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20040025126.pdf [firstpage_image] =>[orig_patent_app_number] => 10212360 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212360
System and method for providing compliant mapping between chip bond locations and package bond locations for an integrated circuit Aug 4, 2002 Issued
Array ( [id] => 7397788 [patent_doc_number] => 20040023127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Correcting a mask pattern using multiple correction grids' [patent_app_type] => new [patent_app_number] => 10/210413 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023127.pdf [firstpage_image] =>[orig_patent_app_number] => 10210413 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/210413
Correcting a mask pattern using multiple correction grids Jul 30, 2002 Issued
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