
Paul Dinh
Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )
| Most Active Art Unit | 2851 |
| Art Unit(s) | 2851, 2816, 2825 |
| Total Applications | 2030 |
| Issued Applications | 1783 |
| Pending Applications | 89 |
| Abandoned Applications | 177 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1218441
[patent_doc_number] => 06711732
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-03-23
[patent_title] => 'Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution era'
[patent_app_type] => B1
[patent_app_number] => 10/205790
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[pdf_file] => patents/06/711/06711732.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/205790 | Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution era | Jul 25, 2002 | Issued |
Array
(
[id] => 7413588
[patent_doc_number] => 20040025125
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-05
[patent_title] => 'CORRECTION OF SPACING VIOLATIONS BETWEEN DESIGN GEOMETRIES AND WIDE CLASS OBJECTS OF DUMMY GEOMETRIES'
[patent_app_type] => new
[patent_app_number] => 10/201071
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/201071 | Correction of spacing violations between design geometries and wide class objects of dummy geometries | Jul 22, 2002 | Issued |
| 10/198940 | EFFICIENT PIPELINING OF SYNTHESIZED SYNCHRONOUS CIRCUITS | Jul 18, 2002 | Abandoned |
Array
(
[id] => 7626790
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[patent_issue_date] => 2004-10-19
[patent_title] => 'Adaptive off tester screening method based on intrinsic die parametric measurements'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/197956 | Adaptive off tester screening method based on intrinsic die parametric measurements | Jul 15, 2002 | Issued |
Array
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[patent_issue_date] => 2003-02-06
[patent_title] => 'High level synthesis method, thread generated using the same, and method for generating circuit including such threads'
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Array
(
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[patent_issue_date] => 2003-03-27
[patent_title] => 'General purpose shape-based layout processing scheme for IC layout modifications\n'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/194703 | General purpose shape-based layout processing scheme for IC layout modificationsn | Jul 11, 2002 | Abandoned |
Array
(
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[patent_title] => 'Construction of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for estimating circuit delay'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/192760 | Construction of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for estimating circuit delay | Jul 8, 2002 | Issued |
Array
(
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[patent_doc_number] => 20030014725
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[patent_issue_date] => 2003-01-16
[patent_title] => 'Electronic circuit designing method and apparatus, and storage medium'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/190721 | Electronic circuit designing method and apparatus, and storage medium | Jul 8, 2002 | Issued |
Array
(
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[patent_title] => 'Controller arrangement for partial reconfiguration of a programmable logic device'
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Array
(
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[patent_title] => 'METHOD AND APPARATUS FOR REDUCING OPTICAL PROXIMITY CORRECTION OUTPUT FILE SIZE'
[patent_app_type] => new
[patent_app_number] => 10/189900
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/189900 | Method and apparatus for reducing optical proximity correction output file size | Jul 2, 2002 | Issued |
Array
(
[id] => 1062339
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[patent_issue_date] => 2005-02-08
[patent_title] => 'Balanced accuracy for extraction'
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[patent_app_number] => 10/064300
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/064300 | Balanced accuracy for extraction | Jun 30, 2002 | Issued |
Array
(
[id] => 7605587
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[patent_title] => 'LSI design system'
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/177992 | Two dimensional compaction system and method | Jun 19, 2002 | Issued |
Array
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Array
(
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