Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1218441 [patent_doc_number] => 06711732 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-23 [patent_title] => 'Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution era' [patent_app_type] => B1 [patent_app_number] => 10/205790 [patent_app_country] => US [patent_app_date] => 2002-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6970 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/711/06711732.pdf [firstpage_image] =>[orig_patent_app_number] => 10205790 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/205790
Full sized scattering bar alt-PSM technique for IC manufacturing in sub-resolution era Jul 25, 2002 Issued
Array ( [id] => 7413588 [patent_doc_number] => 20040025125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'CORRECTION OF SPACING VIOLATIONS BETWEEN DESIGN GEOMETRIES AND WIDE CLASS OBJECTS OF DUMMY GEOMETRIES' [patent_app_type] => new [patent_app_number] => 10/201071 [patent_app_country] => US [patent_app_date] => 2002-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10024 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20040025125.pdf [firstpage_image] =>[orig_patent_app_number] => 10201071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/201071
Correction of spacing violations between design geometries and wide class objects of dummy geometries Jul 22, 2002 Issued
10/198940 EFFICIENT PIPELINING OF SYNTHESIZED SYNCHRONOUS CIRCUITS Jul 18, 2002 Abandoned
Array ( [id] => 7626790 [patent_doc_number] => 06807655 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-19 [patent_title] => 'Adaptive off tester screening method based on intrinsic die parametric measurements' [patent_app_type] => B1 [patent_app_number] => 10/197956 [patent_app_country] => US [patent_app_date] => 2002-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 5408 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/807/06807655.pdf [firstpage_image] =>[orig_patent_app_number] => 10197956 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197956
Adaptive off tester screening method based on intrinsic die parametric measurements Jul 15, 2002 Issued
Array ( [id] => 6717506 [patent_doc_number] => 20030028854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'High level synthesis method, thread generated using the same, and method for generating circuit including such threads' [patent_app_type] => new [patent_app_number] => 10/195740 [patent_app_country] => US [patent_app_date] => 2002-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11775 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028854.pdf [firstpage_image] =>[orig_patent_app_number] => 10195740 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/195740
High level synthesis method, thread generated using the same, and method for generating circuit including such threads Jul 15, 2002 Issued
Array ( [id] => 6675989 [patent_doc_number] => 20030061592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'General purpose shape-based layout processing scheme for IC layout modifications\n' [patent_app_type] => new [patent_app_number] => 10/194703 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7953 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061592.pdf [firstpage_image] =>[orig_patent_app_number] => 10194703 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/194703
General purpose shape-based layout processing scheme for IC layout modificationsn Jul 11, 2002 Abandoned
Array ( [id] => 1139456 [patent_doc_number] => 06789232 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Construction of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for estimating circuit delay' [patent_app_type] => B1 [patent_app_number] => 10/192760 [patent_app_country] => US [patent_app_date] => 2002-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 16668 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789232.pdf [firstpage_image] =>[orig_patent_app_number] => 10192760 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/192760
Construction of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for estimating circuit delay Jul 8, 2002 Issued
Array ( [id] => 6737090 [patent_doc_number] => 20030014725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Electronic circuit designing method and apparatus, and storage medium' [patent_app_type] => new [patent_app_number] => 10/190721 [patent_app_country] => US [patent_app_date] => 2002-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 18291 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 23 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20030014725.pdf [firstpage_image] =>[orig_patent_app_number] => 10190721 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190721
Electronic circuit designing method and apparatus, and storage medium Jul 8, 2002 Issued
Array ( [id] => 1112255 [patent_doc_number] => 06810514 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-26 [patent_title] => 'Controller arrangement for partial reconfiguration of a programmable logic device' [patent_app_type] => B1 [patent_app_number] => 10/188510 [patent_app_country] => US [patent_app_date] => 2002-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5862 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/810/06810514.pdf [firstpage_image] =>[orig_patent_app_number] => 10188510 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/188510
Controller arrangement for partial reconfiguration of a programmable logic device Jul 2, 2002 Issued
Array ( [id] => 7373041 [patent_doc_number] => 20040006756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'METHOD AND APPARATUS FOR REDUCING OPTICAL PROXIMITY CORRECTION OUTPUT FILE SIZE' [patent_app_type] => new [patent_app_number] => 10/189900 [patent_app_country] => US [patent_app_date] => 2002-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3789 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20040006756.pdf [firstpage_image] =>[orig_patent_app_number] => 10189900 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/189900
Method and apparatus for reducing optical proximity correction output file size Jul 2, 2002 Issued
Array ( [id] => 1062339 [patent_doc_number] => 06854099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Balanced accuracy for extraction' [patent_app_type] => utility [patent_app_number] => 10/064300 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4768 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/854/06854099.pdf [firstpage_image] =>[orig_patent_app_number] => 10064300 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064300
Balanced accuracy for extraction Jun 30, 2002 Issued
Array ( [id] => 7605587 [patent_doc_number] => 07100136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'LSI design system' [patent_app_type] => utility [patent_app_number] => 10/183592 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 6177 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/100/07100136.pdf [firstpage_image] =>[orig_patent_app_number] => 10183592 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/183592
LSI design system Jun 27, 2002 Issued
Array ( [id] => 7625670 [patent_doc_number] => 06769097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-27 [patent_title] => 'Scale-invariant topology and traffic allocation in multi-node system-on-chip switching fabrics' [patent_app_type] => B2 [patent_app_number] => 10/185740 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2670 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/769/06769097.pdf [firstpage_image] =>[orig_patent_app_number] => 10185740 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185740
Scale-invariant topology and traffic allocation in multi-node system-on-chip switching fabrics Jun 26, 2002 Issued
Array ( [id] => 6656465 [patent_doc_number] => 20030009728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Two dimensional compaction system and method' [patent_app_type] => new [patent_app_number] => 10/177992 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6538 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20030009728.pdf [firstpage_image] =>[orig_patent_app_number] => 10177992 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/177992
Two dimensional compaction system and method Jun 19, 2002 Issued
Array ( [id] => 1186505 [patent_doc_number] => 06742173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Communication and control model for field programmable gate arrays and other programmable logic devices' [patent_app_type] => B2 [patent_app_number] => 10/175680 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5327 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742173.pdf [firstpage_image] =>[orig_patent_app_number] => 10175680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/175680
Communication and control model for field programmable gate arrays and other programmable logic devices Jun 19, 2002 Issued
Array ( [id] => 6447865 [patent_doc_number] => 20020149399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'High speed low power input buffer' [patent_app_type] => new [patent_app_number] => 10/174206 [patent_app_country] => US [patent_app_date] => 2002-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4751 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149399.pdf [firstpage_image] =>[orig_patent_app_number] => 10174206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/174206
High speed low power input buffer Jun 16, 2002 Issued
Array ( [id] => 1178141 [patent_doc_number] => 06760894 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Method and mechanism for performing improved timing analysis on virtual component blocks' [patent_app_type] => B1 [patent_app_number] => 10/173202 [patent_app_country] => US [patent_app_date] => 2002-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6023 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760894.pdf [firstpage_image] =>[orig_patent_app_number] => 10173202 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/173202
Method and mechanism for performing improved timing analysis on virtual component blocks Jun 13, 2002 Issued
Array ( [id] => 6775550 [patent_doc_number] => 20030018888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'IP validation method and IP verified by the IP validation method' [patent_app_type] => new [patent_app_number] => 10/162061 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6792 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20030018888.pdf [firstpage_image] =>[orig_patent_app_number] => 10162061 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/162061
IP validation method and IP verified by the IP validation method Jun 4, 2002 Issued
Array ( [id] => 726677 [patent_doc_number] => 07051308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Method and apparatus for integrated circuit design with library cells' [patent_app_type] => utility [patent_app_number] => 10/162120 [patent_app_country] => US [patent_app_date] => 2002-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5761 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/051/07051308.pdf [firstpage_image] =>[orig_patent_app_number] => 10162120 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/162120
Method and apparatus for integrated circuit design with library cells Jun 2, 2002 Issued
Array ( [id] => 6661187 [patent_doc_number] => 20030135831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Method and system for creating test component layouts' [patent_app_type] => new [patent_app_number] => 10/160690 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4199 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135831.pdf [firstpage_image] =>[orig_patent_app_number] => 10160690 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/160690
Method and system for creating test component layouts May 30, 2002 Issued
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