Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6798577 [patent_doc_number] => 20030177452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-18 [patent_title] => 'Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed using global and greedy optimizations in combination' [patent_app_type] => new [patent_app_number] => 10/098110 [patent_app_country] => US [patent_app_date] => 2002-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5968 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20030177452.pdf [firstpage_image] =>[orig_patent_app_number] => 10098110 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/098110
Method of optimizing high performance CMOS integrated circuit designs for power consumption and speed using global and greedy optimizations in combination Mar 13, 2002 Issued
Array ( [id] => 1181609 [patent_doc_number] => 06754882 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC)' [patent_app_type] => B1 [patent_app_number] => 10/082440 [patent_app_country] => US [patent_app_date] => 2002-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5608 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754882.pdf [firstpage_image] =>[orig_patent_app_number] => 10082440 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/082440
Method and system for creating a customized support package for an FPGA-based system-on-chip (SoC) Feb 21, 2002 Issued
Array ( [id] => 6181705 [patent_doc_number] => 20020157075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Method and apparatus for computing placement costs' [patent_app_type] => new [patent_app_number] => 10/079270 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 20530 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20020157075.pdf [firstpage_image] =>[orig_patent_app_number] => 10079270 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/079270
Method and apparatus for computing placement costs Feb 19, 2002 Issued
Array ( [id] => 5926901 [patent_doc_number] => 20020116697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Methods for calculating, correcting, and displaying segmented reticle patterns for use in charged-particle-beam microlithography, and screen editors utilizing such methods' [patent_app_type] => new [patent_app_number] => 10/081760 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8810 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116697.pdf [firstpage_image] =>[orig_patent_app_number] => 10081760 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/081760
Methods for calculating, correcting, and displaying segmented reticle patterns for use in charged-particle-beam microlithography, and screen editors utilizing such methods Feb 19, 2002 Abandoned
Array ( [id] => 6707720 [patent_doc_number] => 20030154454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Method and system for estimating jitter in a delay locked loop' [patent_app_type] => new [patent_app_number] => 10/075320 [patent_app_country] => US [patent_app_date] => 2002-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4540 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20030154454.pdf [firstpage_image] =>[orig_patent_app_number] => 10075320 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/075320
Method and system for estimating jitter in a delay locked loop Feb 13, 2002 Issued
Array ( [id] => 6447770 [patent_doc_number] => 20020149392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Level adjustment circuit and data output circuit thereof' [patent_app_type] => new [patent_app_number] => 10/059151 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4093 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149392.pdf [firstpage_image] =>[orig_patent_app_number] => 10059151 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/059151
Level adjustment circuit and data output circuit thereof Jan 30, 2002 Issued
Array ( [id] => 965766 [patent_doc_number] => 06951005 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-27 [patent_title] => 'Method and apparatus for selecting a route for a net based on the impact on other nets' [patent_app_type] => utility [patent_app_number] => 10/066160 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 97 [patent_no_of_words] => 30823 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/951/06951005.pdf [firstpage_image] =>[orig_patent_app_number] => 10066160 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/066160
Method and apparatus for selecting a route for a net based on the impact on other nets Jan 30, 2002 Issued
Array ( [id] => 6853098 [patent_doc_number] => 20030145301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => '2.5-D graph for multi-layer routing' [patent_app_type] => new [patent_app_number] => 10/058550 [patent_app_country] => US [patent_app_date] => 2002-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5674 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20030145301.pdf [firstpage_image] =>[orig_patent_app_number] => 10058550 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/058550
2.5-D graph for multi-layer routing Jan 27, 2002 Issued
Array ( [id] => 6853097 [patent_doc_number] => 20030145300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-31 [patent_title] => 'Layout tracking solutions' [patent_app_type] => new [patent_app_number] => 10/059592 [patent_app_country] => US [patent_app_date] => 2002-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2848 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20030145300.pdf [firstpage_image] =>[orig_patent_app_number] => 10059592 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/059592
Layout tracking solutions Jan 27, 2002 Abandoned
Array ( [id] => 1319594 [patent_doc_number] => 06618849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'Method and apparatus for identifying routes for nets' [patent_app_type] => B2 [patent_app_number] => 10/048000 [patent_app_country] => US [patent_app_date] => 2002-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 74 [patent_figures_cnt] => 96 [patent_no_of_words] => 45025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618849.pdf [firstpage_image] =>[orig_patent_app_number] => 10048000 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/048000
Method and apparatus for identifying routes for nets Jan 12, 2002 Issued
Array ( [id] => 1201177 [patent_doc_number] => 06728939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Method of circuit verification in digital design' [patent_app_type] => B2 [patent_app_number] => 10/038870 [patent_app_country] => US [patent_app_date] => 2002-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 7439 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728939.pdf [firstpage_image] =>[orig_patent_app_number] => 10038870 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038870
Method of circuit verification in digital design Jan 7, 2002 Issued
Array ( [id] => 5861456 [patent_doc_number] => 20020124234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Method for designing circuits with sections having different supply voltages' [patent_app_type] => new [patent_app_number] => 10/040230 [patent_app_country] => US [patent_app_date] => 2002-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5580 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20020124234.pdf [firstpage_image] =>[orig_patent_app_number] => 10040230 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040230
Method for designing circuits with sections having different supply voltages Jan 3, 2002 Issued
Array ( [id] => 999270 [patent_doc_number] => 06915502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'System level applications of adaptive computing (SLAAC) technology' [patent_app_type] => utility [patent_app_number] => 10/038063 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4534 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/915/06915502.pdf [firstpage_image] =>[orig_patent_app_number] => 10038063 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038063
System level applications of adaptive computing (SLAAC) technology Jan 2, 2002 Issued
Array ( [id] => 1060515 [patent_doc_number] => 06848172 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Device and method for package warp compensation in an integrated heat spreader' [patent_app_type] => utility [patent_app_number] => 10/023720 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4866 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/848/06848172.pdf [firstpage_image] =>[orig_patent_app_number] => 10023720 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/023720
Device and method for package warp compensation in an integrated heat spreader Dec 20, 2001 Issued
Array ( [id] => 1396972 [patent_doc_number] => 06567971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Circuit synthesis method using technology parameters extracting circuit' [patent_app_type] => B1 [patent_app_number] => 10/021810 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2894 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567971.pdf [firstpage_image] =>[orig_patent_app_number] => 10021810 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/021810
Circuit synthesis method using technology parameters extracting circuit Dec 19, 2001 Issued
Array ( [id] => 6698112 [patent_doc_number] => 20030110306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Method and system for use of a field programmable gate array (FPGA) cell for controlling access to on-chip functions of a system on a chip (SOC) integrated circuit' [patent_app_type] => new [patent_app_number] => 10/015921 [patent_app_country] => US [patent_app_date] => 2001-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2409 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110306.pdf [firstpage_image] =>[orig_patent_app_number] => 10015921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/015921
Method and system for use of a field programmable gate array (FPGA) cell for controlling access to on-chip functions of a system on a chip (SOC) integrated circuit Dec 9, 2001 Abandoned
Array ( [id] => 6698259 [patent_doc_number] => 20030110453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics' [patent_app_type] => new [patent_app_number] => 10/015920 [patent_app_country] => US [patent_app_date] => 2001-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1927 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20030110453.pdf [firstpage_image] =>[orig_patent_app_number] => 10015920 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/015920
Method and system for use of a field programmable function within a chip to enable configurable I/O signal timing characteristics Dec 9, 2001 Issued
Array ( [id] => 6766931 [patent_doc_number] => 20030101331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'ASIC design technique' [patent_app_type] => new [patent_app_number] => 10/002980 [patent_app_country] => US [patent_app_date] => 2001-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5136 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101331.pdf [firstpage_image] =>[orig_patent_app_number] => 10002980 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002980
ASIC design technique Dec 5, 2001 Abandoned
Array ( [id] => 6205993 [patent_doc_number] => 20020070775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Static timing analysis method for a circuit using generated clock' [patent_app_type] => new [patent_app_number] => 09/987944 [patent_app_country] => US [patent_app_date] => 2001-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6631 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20020070775.pdf [firstpage_image] =>[orig_patent_app_number] => 09987944 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/987944
Static timing analysis method for a circuit using generated clock Nov 15, 2001 Issued
Array ( [id] => 1289581 [patent_doc_number] => 06647538 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Apparatus and method for signal skew characterization utilizing clock division' [patent_app_type] => B1 [patent_app_number] => 10/045473 [patent_app_country] => US [patent_app_date] => 2001-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2532 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647538.pdf [firstpage_image] =>[orig_patent_app_number] => 10045473 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/045473
Apparatus and method for signal skew characterization utilizing clock division Nov 7, 2001 Issued
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