Paul Dinh

Array ( [id] => 1229681 [patent_doc_number] => 06701498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Black box timing model for latch-based systems' [patent_app_type] => B2 [patent_app_number] => 10/008930 [patent_app_country] => US [patent_app_date] => 2001-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 6395 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/701/06701498.pdf [firstpage_image] =>[orig_patent_app_number] => 10008930 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6871727 [patent_doc_number] => 20030084417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Method of designing conductive pattern layout of LSI' [patent_app_type] => new [patent_app_number] => 09/984839 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4218 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20030084417.pdf [firstpage_image] =>[orig_patent_app_number] => 09984839 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1243272 [patent_doc_number] => 06684374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-27 [patent_title] => 'Timing budget designing method' [patent_app_type] => B2 [patent_app_number] => 09/984782 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7388 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/684/06684374.pdf [firstpage_image] =>[orig_patent_app_number] => 09984782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1444237 [patent_doc_number] => 06496970 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Signal routing in programmable logic devices' [patent_app_type] => B1 [patent_app_number] => 10/035500 [patent_app_country] => US [patent_app_date] => 2001-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3022 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496970.pdf [firstpage_image] =>[orig_patent_app_number] => 10035500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1425765 [patent_doc_number] => 06536014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Reusable configuration tool' [patent_app_type] => B1 [patent_app_number] => 09/964300 [patent_app_country] => US [patent_app_date] => 2001-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 5394 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/536/06536014.pdf [firstpage_image] =>[orig_patent_app_number] => 09964300 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1417588 [patent_doc_number] => 06532570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Designing integrated circuits to reduce temperature induced electromigration effects' [patent_app_type] => B1 [patent_app_number] => 09/949067 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5576 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532570.pdf [firstpage_image] =>[orig_patent_app_number] => 09949067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1378020 [patent_doc_number] => 06578178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-10 [patent_title] => 'Designing integrated circuits to reduce electromigration effects' [patent_app_type] => B2 [patent_app_number] => 09/949068 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5448 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578178.pdf [firstpage_image] =>[orig_patent_app_number] => 09949068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1506152 [patent_doc_number] => 06487705 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Timing optimization and timing closure for integrated circuit models' [patent_app_type] => B1 [patent_app_number] => 09/946240 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4944 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487705.pdf [firstpage_image] =>[orig_patent_app_number] => 09946240 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1348937 [patent_doc_number] => 06598212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-22 [patent_title] => 'Delay circuit, testing apparatus, and capacitor' [patent_app_type] => B2 [patent_app_number] => 09/942355 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3487 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598212.pdf [firstpage_image] =>[orig_patent_app_number] => 09942355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1366133 [patent_doc_number] => 06581200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-17 [patent_title] => 'Abstracting netlist to manage routing information' [patent_app_type] => B2 [patent_app_number] => 09/932747 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3305 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581200.pdf [firstpage_image] =>[orig_patent_app_number] => 09932747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1366098 [patent_doc_number] => 06581197 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Minimal level sensitive timing representative of a circuit path' [patent_app_type] => B1 [patent_app_number] => 09/927856 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581197.pdf [firstpage_image] =>[orig_patent_app_number] => 09927856 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1337706 [patent_doc_number] => 06604227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Minimal level sensitive timing abstraction model capable of being used in general static timing analysis tools' [patent_app_type] => B1 [patent_app_number] => 09/928161 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 11199 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604227.pdf [firstpage_image] =>[orig_patent_app_number] => 09928161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1324467 [patent_doc_number] => 06611948 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-26 [patent_title] => 'Modeling circuit environmental sensitivity of a minimal level sensitive timing abstraction model' [patent_app_type] => B1 [patent_app_number] => 09/927220 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8378 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611948.pdf [firstpage_image] =>[orig_patent_app_number] => 09927220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1327204 [patent_doc_number] => 06609233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Load sensitivity modeling in a minimal level sensitive timing abstraction model' [patent_app_type] => B1 [patent_app_number] => 09/927857 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9251 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/609/06609233.pdf [firstpage_image] =>[orig_patent_app_number] => 09927857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 771696 [patent_doc_number] => 07010767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Insertion of repeaters without timing constraints' [patent_app_type] => utility [patent_app_number] => 09/919740 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7273 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010767.pdf [firstpage_image] =>[orig_patent_app_number] => 09919740 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1533400 [patent_doc_number] => 06480999 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Signal routing in programmable logic devices' [patent_app_type] => B1 [patent_app_number] => 09/916071 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3020 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480999.pdf [firstpage_image] =>[orig_patent_app_number] => 09916071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1408054 [patent_doc_number] => 06560756 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method and apparatus for distributed test pattern decompression' [patent_app_type] => B1 [patent_app_number] => 09/898160 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4951 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560756.pdf [firstpage_image] =>[orig_patent_app_number] => 09898160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5910699 [patent_doc_number] => 20020144232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Alleviating line end shortening in transistor endcaps by extending phase shifters' [patent_app_type] => new [patent_app_number] => 09/872620 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2452 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20020144232.pdf [firstpage_image] =>[orig_patent_app_number] => 09872620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431248 [patent_doc_number] => 06507939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Net delay optimization with ramptime violation removal' [patent_app_type] => B1 [patent_app_number] => 09/858166 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5177 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507939.pdf [firstpage_image] =>[orig_patent_app_number] => 09858166 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6920784 [patent_doc_number] => 20010028269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Method and apparatus for reducing the vulnerability of latches to single event upsets' [patent_app_type] => new [patent_app_number] => 09/840684 [patent_app_country] => US [patent_app_date] => 2001-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8257 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20010028269.pdf [firstpage_image] =>[orig_patent_app_number] => 09840684 [rel_patent_id] =>[rel_patent_doc_number] =>)