Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 705953 [patent_doc_number] => 07069524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-27 [patent_title] => 'Method and device for analyzing a network of conductors' [patent_app_type] => utility [patent_app_number] => 10/257910 [patent_app_country] => US [patent_app_date] => 2001-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/069/07069524.pdf [firstpage_image] =>[orig_patent_app_number] => 10257910 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/257910
Method and device for analyzing a network of conductors Apr 17, 2001 Issued
Array ( [id] => 1285208 [patent_doc_number] => 06651238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Providing fault coverage of interconnect in an FPGA' [patent_app_type] => B1 [patent_app_number] => 09/837380 [patent_app_country] => US [patent_app_date] => 2001-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651238.pdf [firstpage_image] =>[orig_patent_app_number] => 09837380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/837380
Providing fault coverage of interconnect in an FPGA Apr 16, 2001 Issued
Array ( [id] => 1001865 [patent_doc_number] => 06912703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Structure of integrated circuit standard cell library for reducing power supply voltage fluctuation' [patent_app_type] => utility [patent_app_number] => 09/809830 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2423 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912703.pdf [firstpage_image] =>[orig_patent_app_number] => 09809830 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809830
Structure of integrated circuit standard cell library for reducing power supply voltage fluctuation Mar 18, 2001 Issued
Array ( [id] => 6901160 [patent_doc_number] => 20010022743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-20 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 09/803030 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13317 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20010022743.pdf [firstpage_image] =>[orig_patent_app_number] => 09803030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803030
Semiconductor integrated circuit device Mar 11, 2001 Issued
Array ( [id] => 6418676 [patent_doc_number] => 20020126029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Programmable test modulator for selectively generating test signals of delta-sigma order N' [patent_app_type] => new [patent_app_number] => 09/803350 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 7559 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20020126029.pdf [firstpage_image] =>[orig_patent_app_number] => 09803350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803350
Programmable test modulator for selectively generating test signals of delta-sigma order N Mar 7, 2001 Abandoned
Array ( [id] => 6181667 [patent_doc_number] => 20020157064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Hierarchical metal one usage tool for child level leaf cell' [patent_app_type] => new [patent_app_number] => 09/784662 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3812 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20020157064.pdf [firstpage_image] =>[orig_patent_app_number] => 09784662 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/784662
Hierarchical metal one usage tool for child level leaf cell Feb 14, 2001 Issued
Array ( [id] => 1297435 [patent_doc_number] => 06634011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Method and apparatus for recording program execution in a microprocessor based integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/788195 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/634/06634011.pdf [firstpage_image] =>[orig_patent_app_number] => 09788195 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/788195
Method and apparatus for recording program execution in a microprocessor based integrated circuit Feb 14, 2001 Issued
Array ( [id] => 6138647 [patent_doc_number] => 20020000859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Method and apparatus for single-ended sense amplifier and biasing' [patent_app_type] => new [patent_app_number] => 09/775453 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4668 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20020000859.pdf [firstpage_image] =>[orig_patent_app_number] => 09775453 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/775453
Method and apparatus for single-ended sense amplifier and biasing Jan 31, 2001 Abandoned
Array ( [id] => 1603444 [patent_doc_number] => 06433626 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Current-mode filter with complex zeros' [patent_app_type] => B1 [patent_app_number] => 09/761085 [patent_app_country] => US [patent_app_date] => 2001-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3619 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433626.pdf [firstpage_image] =>[orig_patent_app_number] => 09761085 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/761085
Current-mode filter with complex zeros Jan 15, 2001 Issued
Array ( [id] => 5886398 [patent_doc_number] => 20020011890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => new [patent_app_number] => 09/756215 [patent_app_country] => US [patent_app_date] => 2001-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6497 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20020011890.pdf [firstpage_image] =>[orig_patent_app_number] => 09756215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/756215
Semiconductor integrated circuit Jan 8, 2001 Issued
Array ( [id] => 1544906 [patent_doc_number] => 06373297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Input buffer capable of achieving quick response' [patent_app_type] => B1 [patent_app_number] => 09/756213 [patent_app_country] => US [patent_app_date] => 2001-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3628 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373297.pdf [firstpage_image] =>[orig_patent_app_number] => 09756213 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/756213
Input buffer capable of achieving quick response Jan 8, 2001 Issued
Array ( [id] => 1516633 [patent_doc_number] => 06420925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Programmable latch device with integrated programmable element' [patent_app_type] => B1 [patent_app_number] => 09/757267 [patent_app_country] => US [patent_app_date] => 2001-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4235 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420925.pdf [firstpage_image] =>[orig_patent_app_number] => 09757267 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/757267
Programmable latch device with integrated programmable element Jan 8, 2001 Issued
Array ( [id] => 1462152 [patent_doc_number] => 06392449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'High-speed low-power low-offset hybrid comparator' [patent_app_type] => B1 [patent_app_number] => 09/755551 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4311 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392449.pdf [firstpage_image] =>[orig_patent_app_number] => 09755551 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755551
High-speed low-power low-offset hybrid comparator Jan 4, 2001 Issued
Array ( [id] => 6578675 [patent_doc_number] => 20020084825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Small swing output buffer for reducing EMI' [patent_app_type] => new [patent_app_number] => 09/754455 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2093 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20020084825.pdf [firstpage_image] =>[orig_patent_app_number] => 09754455 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/754455
Small swing output buffer for reducing EMI Jan 3, 2001 Abandoned
Array ( [id] => 6881860 [patent_doc_number] => 20010048332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Vcc-compensated bus-hold circuit' [patent_app_type] => new [patent_app_number] => 09/754514 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2744 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20010048332.pdf [firstpage_image] =>[orig_patent_app_number] => 09754514 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/754514
Vcc-compensated bus-hold circuit Jan 3, 2001 Issued
Array ( [id] => 6578703 [patent_doc_number] => 20020084826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Reduced current variability I/O bus termination' [patent_app_type] => new [patent_app_number] => 09/754667 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1725 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20020084826.pdf [firstpage_image] =>[orig_patent_app_number] => 09754667 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/754667
Reduced current variability I/O bus termination Jan 3, 2001 Issued
Array ( [id] => 6578978 [patent_doc_number] => 20020084838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'RAIL-TO-RAIL INPUT CLOCKED AMPLIFIER' [patent_app_type] => new [patent_app_number] => 09/752647 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2108 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20020084838.pdf [firstpage_image] =>[orig_patent_app_number] => 09752647 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752647
Rail-to-rail input clocked amplifier Dec 28, 2000 Issued
Array ( [id] => 4336493 [patent_doc_number] => 06320426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Self-calibrating circuit of high speed comparator' [patent_app_type] => 1 [patent_app_number] => 9/750461 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2945 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 631 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320426.pdf [firstpage_image] =>[orig_patent_app_number] => 750461 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750461
Self-calibrating circuit of high speed comparator Dec 27, 2000 Issued
Array ( [id] => 6815065 [patent_doc_number] => 20030074615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Weighted random pattern test using pre-stored weights' [patent_app_type] => new [patent_app_number] => 09/750200 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4065 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074615.pdf [firstpage_image] =>[orig_patent_app_number] => 09750200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750200
Weighted random pattern test using pre-stored weights Dec 26, 2000 Issued
Array ( [id] => 7635888 [patent_doc_number] => 06380772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Self-limiting pad driver' [patent_app_type] => B1 [patent_app_number] => 09/746687 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 7145 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380772.pdf [firstpage_image] =>[orig_patent_app_number] => 09746687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746687
Self-limiting pad driver Dec 21, 2000 Issued
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