Paul Dinh

Array ( [id] => 1120176 [patent_doc_number] => 06802049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Method and apparatus for computing placement costs by calculating bend values of connection graphs that model interconnect line topologies' [patent_app_type] => B2 [patent_app_number] => 09/739460 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 50 [patent_no_of_words] => 23716 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/802/06802049.pdf [firstpage_image] =>[orig_patent_app_number] => 09739460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1419773 [patent_doc_number] => 06546539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Netlist resynthesis program using structure co-factoring' [patent_app_type] => B1 [patent_app_number] => 09/736571 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4697 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546539.pdf [firstpage_image] =>[orig_patent_app_number] => 09736571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6732096 [patent_doc_number] => 20030188286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Method and Apparatus for Using a Diagona Line to Measure Congestion in a Region of an Integrated-Circuit Layout' [patent_app_type] => new [patent_app_number] => 09/737220 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 15337 [patent_no_of_claims] => 87 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20030188286.pdf [firstpage_image] =>[orig_patent_app_number] => 09737220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1329496 [patent_doc_number] => 06606732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-12 [patent_title] => 'Method for specifying, identifying, selecting or verifying differential signal pairs on IC packages' [patent_app_type] => B2 [patent_app_number] => 09/734515 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3607 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/606/06606732.pdf [firstpage_image] =>[orig_patent_app_number] => 09734515 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6211727 [patent_doc_number] => 20020073388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Methodology to improve the performance of integrated circuits by exploiting systematic process non-uniformity' [patent_app_type] => new [patent_app_number] => 09/733411 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4429 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073388.pdf [firstpage_image] =>[orig_patent_app_number] => 09733411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6908596 [patent_doc_number] => 20010011363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'Circuit synthesis method' [patent_app_type] => new [patent_app_number] => 09/728075 [patent_app_country] => US [patent_app_date] => 2000-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5373 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20010011363.pdf [firstpage_image] =>[orig_patent_app_number] => 09728075 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7631481 [patent_doc_number] => 06665856 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Displacing edge segments on a fabrication layout based on proximity effects model amplitudes for correcting proximity effects' [patent_app_type] => B1 [patent_app_number] => 09/728885 [patent_app_country] => US [patent_app_date] => 2000-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17583 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665856.pdf [firstpage_image] =>[orig_patent_app_number] => 09728885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6899340 [patent_doc_number] => 20010047505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'High Q gyrator structures' [patent_app_type] => new [patent_app_number] => 09/726908 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 10443 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20010047505.pdf [firstpage_image] =>[orig_patent_app_number] => 09726908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6633024 [patent_doc_number] => 20020066067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Low leakage antenna diode insertion for integrated circuits' [patent_app_type] => new [patent_app_number] => 09/725825 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2804 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066067.pdf [firstpage_image] =>[orig_patent_app_number] => 09725825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6633029 [patent_doc_number] => 20020066068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Printed circuit board design, testing, and manufacturing process' [patent_app_type] => new [patent_app_number] => 09/725389 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4557 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20020066068.pdf [firstpage_image] =>[orig_patent_app_number] => 09725389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1357925 [patent_doc_number] => 06591405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Clustering for data compression' [patent_app_type] => B1 [patent_app_number] => 09/727531 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7794 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591405.pdf [firstpage_image] =>[orig_patent_app_number] => 09727531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1354128 [patent_doc_number] => 06594802 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Method and apparatus for providing optimized access to circuits for debug, programming, and test' [patent_app_type] => B1 [patent_app_number] => 09/716583 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12472 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594802.pdf [firstpage_image] =>[orig_patent_app_number] => 09716583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1419785 [patent_doc_number] => 06546540 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method of automatic layout design for LSI, mask set and semiconductor integrated circuit manufactured by automatic layout design method, and recording medium storing automatic layout design program' [patent_app_type] => B1 [patent_app_number] => 09/713050 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 50 [patent_no_of_words] => 13173 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546540.pdf [firstpage_image] =>[orig_patent_app_number] => 09713050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1429452 [patent_doc_number] => 06513146 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Method of designing semiconductor integrated circuit device, method of analyzing power consumption of circuit and apparatus for analyzing power consumption' [patent_app_type] => B1 [patent_app_number] => 09/711885 [patent_app_country] => US [patent_app_date] => 2000-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 74 [patent_no_of_words] => 18770 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513146.pdf [firstpage_image] =>[orig_patent_app_number] => 09711885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1226005 [patent_doc_number] => 06704908 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Method and apparatus for automatically generating a phase lock loop (PLL)' [patent_app_type] => B1 [patent_app_number] => 09/707330 [patent_app_country] => US [patent_app_date] => 2000-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 12620 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704908.pdf [firstpage_image] =>[orig_patent_app_number] => 09707330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1502838 [patent_doc_number] => 06486711 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Capacitor-based exponential programmable gain amplifier' [patent_app_type] => B1 [patent_app_number] => 09/705649 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4022 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486711.pdf [firstpage_image] =>[orig_patent_app_number] => 09705649 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1495697 [patent_doc_number] => 06342800 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Charge compensation control circuit and method for use with output driver' [patent_app_type] => B1 [patent_app_number] => 09/698997 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 9147 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/342/06342800.pdf [firstpage_image] =>[orig_patent_app_number] => 09698997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1479216 [patent_doc_number] => 06344773 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Flexible monolithic continuous-time analog low-pass filter with minimal circuitry' [patent_app_type] => B1 [patent_app_number] => 09/693058 [patent_app_country] => US [patent_app_date] => 2000-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3949 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344773.pdf [firstpage_image] =>[orig_patent_app_number] => 09693058 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1472246 [patent_doc_number] => 06407601 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Delay cell' [patent_app_type] => B1 [patent_app_number] => 09/684698 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 7620 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407601.pdf [firstpage_image] =>[orig_patent_app_number] => 09684698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1093045 [patent_doc_number] => 06829751 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-07 [patent_title] => 'Diagnostic architecture using FPGA core in system on a chip design' [patent_app_type] => B1 [patent_app_number] => 09/684868 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3433 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829751.pdf [firstpage_image] =>[orig_patent_app_number] => 09684868 [rel_patent_id] =>[rel_patent_doc_number] =>)