Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1431516 [patent_doc_number] => 06523162 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'General purpose shape-based layout processing scheme for IC layout modifications' [patent_app_type] => B1 [patent_app_number] => 09/632080 [patent_app_country] => US [patent_app_date] => 2000-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 33 [patent_no_of_words] => 7801 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523162.pdf [firstpage_image] =>[orig_patent_app_number] => 09632080 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632080
General purpose shape-based layout processing scheme for IC layout modifications Aug 1, 2000 Issued
Array ( [id] => 1460254 [patent_doc_number] => 06463570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Apparatus and method for verifying process integrity' [patent_app_type] => B1 [patent_app_number] => 09/625620 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4185 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463570.pdf [firstpage_image] =>[orig_patent_app_number] => 09625620 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/625620
Apparatus and method for verifying process integrity Jul 25, 2000 Issued
Array ( [id] => 1533386 [patent_doc_number] => 06480996 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'System and method for transposing wires in a circuit design' [patent_app_type] => B1 [patent_app_number] => 09/610746 [patent_app_country] => US [patent_app_date] => 2000-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3899 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480996.pdf [firstpage_image] =>[orig_patent_app_number] => 09610746 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/610746
System and method for transposing wires in a circuit design Jul 5, 2000 Issued
Array ( [id] => 1419720 [patent_doc_number] => 06546534 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => B1 [patent_app_number] => 09/610767 [patent_app_country] => US [patent_app_date] => 2000-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5164 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546534.pdf [firstpage_image] =>[orig_patent_app_number] => 09610767 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/610767
Semiconductor integrated circuit device Jul 5, 2000 Issued
Array ( [id] => 1432020 [patent_doc_number] => 06516451 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Standards-integrated design software' [patent_app_type] => B1 [patent_app_number] => 09/610851 [patent_app_country] => US [patent_app_date] => 2000-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3104 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516451.pdf [firstpage_image] =>[orig_patent_app_number] => 09610851 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/610851
Standards-integrated design software Jul 4, 2000 Issued
Array ( [id] => 1506167 [patent_doc_number] => 06487710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Method and apparatus for assigning PLD signal routes to input signals having different voltage requirements' [patent_app_type] => B1 [patent_app_number] => 09/608269 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3783 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487710.pdf [firstpage_image] =>[orig_patent_app_number] => 09608269 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/608269
Method and apparatus for assigning PLD signal routes to input signals having different voltage requirements Jun 29, 2000 Issued
Array ( [id] => 1396992 [patent_doc_number] => 06567972 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method and apparatus for correcting mask pattern, mask having corrected mask pattern, and storage medium storing program for executing the method for correcting mask pattern' [patent_app_type] => B1 [patent_app_number] => 09/609715 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4514 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567972.pdf [firstpage_image] =>[orig_patent_app_number] => 09609715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609715
Method and apparatus for correcting mask pattern, mask having corrected mask pattern, and storage medium storing program for executing the method for correcting mask pattern Jun 29, 2000 Issued
Array ( [id] => 1348868 [patent_doc_number] => 06598207 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Software for converting power delivery interconnect modeling connectivity maps to simulation ready input' [patent_app_type] => B1 [patent_app_number] => 09/608680 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5312 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598207.pdf [firstpage_image] =>[orig_patent_app_number] => 09608680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/608680
Software for converting power delivery interconnect modeling connectivity maps to simulation ready input Jun 28, 2000 Issued
Array ( [id] => 1412892 [patent_doc_number] => 06553545 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Process parameter extraction' [patent_app_type] => B1 [patent_app_number] => 09/606484 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6097 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553545.pdf [firstpage_image] =>[orig_patent_app_number] => 09606484 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/606484
Process parameter extraction Jun 28, 2000 Issued
Array ( [id] => 1292524 [patent_doc_number] => 06643839 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Determining an optimum wiring pattern and component placement scheme for a printed wiring board' [patent_app_type] => B1 [patent_app_number] => 09/605616 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4271 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643839.pdf [firstpage_image] =>[orig_patent_app_number] => 09605616 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/605616
Determining an optimum wiring pattern and component placement scheme for a printed wiring board Jun 27, 2000 Issued
Array ( [id] => 1501800 [patent_doc_number] => 06405351 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'System for verifying leaf-cell circuit properties' [patent_app_type] => B1 [patent_app_number] => 09/603708 [patent_app_country] => US [patent_app_date] => 2000-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 13328 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405351.pdf [firstpage_image] =>[orig_patent_app_number] => 09603708 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603708
System for verifying leaf-cell circuit properties Jun 26, 2000 Issued
Array ( [id] => 1448672 [patent_doc_number] => 06369627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Delay circuit and semiconductor integrated circuit having same' [patent_app_type] => B1 [patent_app_number] => 09/604247 [patent_app_country] => US [patent_app_date] => 2000-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 74 [patent_figures_cnt] => 74 [patent_no_of_words] => 36177 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369627.pdf [firstpage_image] =>[orig_patent_app_number] => 09604247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/604247
Delay circuit and semiconductor integrated circuit having same Jun 26, 2000 Issued
Array ( [id] => 7635876 [patent_doc_number] => 06380784 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Circuit for generating sense amplifier control signal for semiconductor memory' [patent_app_type] => B1 [patent_app_number] => 09/599614 [patent_app_country] => US [patent_app_date] => 2000-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3148 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380784.pdf [firstpage_image] =>[orig_patent_app_number] => 09599614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/599614
Circuit for generating sense amplifier control signal for semiconductor memory Jun 22, 2000 Issued
Array ( [id] => 1472157 [patent_doc_number] => 06460172 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Microprocessor based mixed signal field programmable integrated device and prototyping methodology' [patent_app_type] => B1 [patent_app_number] => 09/598588 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3017 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460172.pdf [firstpage_image] =>[orig_patent_app_number] => 09598588 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/598588
Microprocessor based mixed signal field programmable integrated device and prototyping methodology Jun 20, 2000 Issued
Array ( [id] => 1596180 [patent_doc_number] => 06484300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Systems, methods and computer program products for obtaining an effective pattern density of a layer in an integrated circuit, and for simulating a chemical-mechanical polishing process using the same' [patent_app_type] => B1 [patent_app_number] => 09/597120 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 8233 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484300.pdf [firstpage_image] =>[orig_patent_app_number] => 09597120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597120
Systems, methods and computer program products for obtaining an effective pattern density of a layer in an integrated circuit, and for simulating a chemical-mechanical polishing process using the same Jun 19, 2000 Issued
Array ( [id] => 1419702 [patent_doc_number] => 06546532 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Method and apparatus for traversing and placing cells using a placement tool' [patent_app_type] => B1 [patent_app_number] => 09/597978 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 12610 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546532.pdf [firstpage_image] =>[orig_patent_app_number] => 09597978 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597978
Method and apparatus for traversing and placing cells using a placement tool Jun 19, 2000 Issued
Array ( [id] => 1476869 [patent_doc_number] => 06388486 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Load sensing, slew rate shaping, output signal pad cell driver circuit and method' [patent_app_type] => B1 [patent_app_number] => 09/596568 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 78 [patent_no_of_words] => 13888 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388486.pdf [firstpage_image] =>[orig_patent_app_number] => 09596568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596568
Load sensing, slew rate shaping, output signal pad cell driver circuit and method Jun 18, 2000 Issued
Array ( [id] => 4412136 [patent_doc_number] => 06271688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'MOS transconductor with broad trimming range' [patent_app_type] => 1 [patent_app_number] => 9/596510 [patent_app_country] => US [patent_app_date] => 2000-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1268 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271688.pdf [firstpage_image] =>[orig_patent_app_number] => 596510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/596510
MOS transconductor with broad trimming range Jun 18, 2000 Issued
Array ( [id] => 4379116 [patent_doc_number] => 06288603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'High-voltage bidirectional switch made using high-voltage MOS transistors' [patent_app_type] => 1 [patent_app_number] => 9/595680 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4092 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288603.pdf [firstpage_image] =>[orig_patent_app_number] => 595680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595680
High-voltage bidirectional switch made using high-voltage MOS transistors Jun 15, 2000 Issued
Array ( [id] => 4334137 [patent_doc_number] => 06329862 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Reference frequency signal switching circuit capable of adjusting level of external reference frequency signal and outputting resultant signal' [patent_app_type] => 1 [patent_app_number] => 9/595710 [patent_app_country] => US [patent_app_date] => 2000-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6878 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329862.pdf [firstpage_image] =>[orig_patent_app_number] => 595710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/595710
Reference frequency signal switching circuit capable of adjusting level of external reference frequency signal and outputting resultant signal Jun 15, 2000 Issued
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