Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1429473 [patent_doc_number] => 06513149 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Routing balanced clock signals' [patent_app_type] => B1 [patent_app_number] => 09/540273 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3488 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513149.pdf [firstpage_image] =>[orig_patent_app_number] => 09540273 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/540273
Routing balanced clock signals Mar 30, 2000 Issued
Array ( [id] => 1585137 [patent_doc_number] => 06449754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Method of measuring the accuracy of parasitic capacitance extraction' [patent_app_type] => B1 [patent_app_number] => 09/534280 [patent_app_country] => US [patent_app_date] => 2000-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3306 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449754.pdf [firstpage_image] =>[orig_patent_app_number] => 09534280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/534280
Method of measuring the accuracy of parasitic capacitance extraction Mar 23, 2000 Issued
Array ( [id] => 7635866 [patent_doc_number] => 06380794 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Hybrid circuit having current source controlled by a comparator' [patent_app_type] => B1 [patent_app_number] => 09/534522 [patent_app_country] => US [patent_app_date] => 2000-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2016 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380794.pdf [firstpage_image] =>[orig_patent_app_number] => 09534522 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/534522
Hybrid circuit having current source controlled by a comparator Mar 23, 2000 Issued
Array ( [id] => 1562628 [patent_doc_number] => 06437635 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Amplification type solid states imaging device output circuit capable of stably operating at a low voltage' [patent_app_type] => B1 [patent_app_number] => 09/532256 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7078 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/437/06437635.pdf [firstpage_image] =>[orig_patent_app_number] => 09532256 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/532256
Amplification type solid states imaging device output circuit capable of stably operating at a low voltage Mar 21, 2000 Issued
Array ( [id] => 1485307 [patent_doc_number] => 06453456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'System and method for interactive implementation and testing of logic cores on a programmable logic device' [patent_app_type] => B1 [patent_app_number] => 09/533091 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3571 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453456.pdf [firstpage_image] =>[orig_patent_app_number] => 09533091 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/533091
System and method for interactive implementation and testing of logic cores on a programmable logic device Mar 21, 2000 Issued
Array ( [id] => 1506158 [patent_doc_number] => 06487707 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'LAYOUT DESIGN SYSTEM OF SEMICONDUCTOR IC DEVICE, LAYOUT DESIGN METHOD OF SEMICONDUCTOR IC DEVICE AND COMPUTER-READABLE RECORDING MEDIUM ON WHICH PROGRAMS FOR ALLOWING COMPUTER TO EXECUTE RESPECTIVE MEANS IN THE SYSTEM OR RESPECTIVE STEPS IN THE METHOD ARE RECORDED' [patent_app_type] => B1 [patent_app_number] => 09/533171 [patent_app_country] => US [patent_app_date] => 2000-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6617 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/487/06487707.pdf [firstpage_image] =>[orig_patent_app_number] => 09533171 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/533171
LAYOUT DESIGN SYSTEM OF SEMICONDUCTOR IC DEVICE, LAYOUT DESIGN METHOD OF SEMICONDUCTOR IC DEVICE AND COMPUTER-READABLE RECORDING MEDIUM ON WHICH PROGRAMS FOR ALLOWING COMPUTER TO EXECUTE RESPECTIVE MEANS IN THE SYSTEM OR RESPECTIVE STEPS IN THE METHOD ARE RECORDED Mar 21, 2000 Issued
Array ( [id] => 1539458 [patent_doc_number] => 06412099 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Apparatus and method for converting logical connection information of circuit' [patent_app_type] => B1 [patent_app_number] => 09/531832 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5219 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412099.pdf [firstpage_image] =>[orig_patent_app_number] => 09531832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531832
Apparatus and method for converting logical connection information of circuit Mar 20, 2000 Issued
Array ( [id] => 1509187 [patent_doc_number] => 06467074 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Integrated circuit architecture with standard blocks' [patent_app_type] => B1 [patent_app_number] => 09/532330 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 12594 [patent_no_of_claims] => 100 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467074.pdf [firstpage_image] =>[orig_patent_app_number] => 09532330 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/532330
Integrated circuit architecture with standard blocks Mar 20, 2000 Issued
Array ( [id] => 1469100 [patent_doc_number] => 06459322 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Level adjustment circuit and data output circuit thereof' [patent_app_type] => B1 [patent_app_number] => 09/531669 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4066 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459322.pdf [firstpage_image] =>[orig_patent_app_number] => 09531669 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531669
Level adjustment circuit and data output circuit thereof Mar 19, 2000 Issued
Array ( [id] => 7629922 [patent_doc_number] => 06637017 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Real time programmable feature control for programmable logic devices' [patent_app_type] => B1 [patent_app_number] => 09/527715 [patent_app_country] => US [patent_app_date] => 2000-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2647 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/637/06637017.pdf [firstpage_image] =>[orig_patent_app_number] => 09527715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/527715
Real time programmable feature control for programmable logic devices Mar 16, 2000 Issued
Array ( [id] => 1604542 [patent_doc_number] => 06434728 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Activation path simulation equipment and activation path simulation method' [patent_app_type] => B1 [patent_app_number] => 09/527296 [patent_app_country] => US [patent_app_date] => 2000-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 5961 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434728.pdf [firstpage_image] =>[orig_patent_app_number] => 09527296 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/527296
Activation path simulation equipment and activation path simulation method Mar 16, 2000 Issued
Array ( [id] => 4361489 [patent_doc_number] => 06292036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Drive circuit' [patent_app_type] => 1 [patent_app_number] => 9/525351 [patent_app_country] => US [patent_app_date] => 2000-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4132 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292036.pdf [firstpage_image] =>[orig_patent_app_number] => 525351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/525351
Drive circuit Mar 14, 2000 Issued
Array ( [id] => 1513515 [patent_doc_number] => 06442735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'SOI circuit design method' [patent_app_type] => B1 [patent_app_number] => 09/525363 [patent_app_country] => US [patent_app_date] => 2000-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4859 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442735.pdf [firstpage_image] =>[orig_patent_app_number] => 09525363 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/525363
SOI circuit design method Mar 14, 2000 Issued
Array ( [id] => 1569175 [patent_doc_number] => 06377097 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method and apparatus for reducing the vulnerability of latches to single event upsets' [patent_app_type] => B1 [patent_app_number] => 09/525371 [patent_app_country] => US [patent_app_date] => 2000-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 30 [patent_no_of_words] => 8171 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377097.pdf [firstpage_image] =>[orig_patent_app_number] => 09525371 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/525371
Method and apparatus for reducing the vulnerability of latches to single event upsets Mar 12, 2000 Issued
Array ( [id] => 1408020 [patent_doc_number] => 06560754 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method and apparatus for jump control in a pipelined processor' [patent_app_type] => B1 [patent_app_number] => 09/523871 [patent_app_country] => US [patent_app_date] => 2000-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8235 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560754.pdf [firstpage_image] =>[orig_patent_app_number] => 09523871 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/523871
Method and apparatus for jump control in a pipelined processor Mar 12, 2000 Issued
Array ( [id] => 1495521 [patent_doc_number] => 06418553 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Circuit designing method for semiconductor device and computer-readable medium' [patent_app_type] => B1 [patent_app_number] => 09/522951 [patent_app_country] => US [patent_app_date] => 2000-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4482 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418553.pdf [firstpage_image] =>[orig_patent_app_number] => 09522951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/522951
Circuit designing method for semiconductor device and computer-readable medium Mar 9, 2000 Issued
Array ( [id] => 1362355 [patent_doc_number] => 06587994 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Hot-carrier degradation simulation of a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/523062 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 9091 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587994.pdf [firstpage_image] =>[orig_patent_app_number] => 09523062 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/523062
Hot-carrier degradation simulation of a semiconductor device Mar 8, 2000 Issued
Array ( [id] => 1476906 [patent_doc_number] => 06388498 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Semiconductor device capable of reducing noise' [patent_app_type] => B1 [patent_app_number] => 09/522360 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4156 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388498.pdf [firstpage_image] =>[orig_patent_app_number] => 09522360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/522360
Semiconductor device capable of reducing noise Mar 8, 2000 Issued
Array ( [id] => 4416096 [patent_doc_number] => 06229356 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Stabilized gate drivers' [patent_app_type] => 1 [patent_app_number] => 9/522077 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2279 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229356.pdf [firstpage_image] =>[orig_patent_app_number] => 522077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/522077
Stabilized gate drivers Mar 8, 2000 Issued
Array ( [id] => 1472139 [patent_doc_number] => 06460165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Model for simulating tree structured VLSI interconnect' [patent_app_type] => B1 [patent_app_number] => 09/521178 [patent_app_country] => US [patent_app_date] => 2000-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 34 [patent_no_of_words] => 8339 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460165.pdf [firstpage_image] =>[orig_patent_app_number] => 09521178 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/521178
Model for simulating tree structured VLSI interconnect Mar 7, 2000 Issued
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