Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1521910 [patent_doc_number] => 06502227 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'LSI design method which never produces timing error having influence on entire specification of LSI function, after design of layout and circuit of detailed portion' [patent_app_type] => B1 [patent_app_number] => 09/518906 [patent_app_country] => US [patent_app_date] => 2000-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5968 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502227.pdf [firstpage_image] =>[orig_patent_app_number] => 09518906 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/518906
LSI design method which never produces timing error having influence on entire specification of LSI function, after design of layout and circuit of detailed portion Mar 2, 2000 Issued
Array ( [id] => 1396641 [patent_doc_number] => 06567955 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Method and system for approximating distributed constant line' [patent_app_type] => B1 [patent_app_number] => 09/486820 [patent_app_country] => US [patent_app_date] => 2000-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 8757 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567955.pdf [firstpage_image] =>[orig_patent_app_number] => 09486820 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/486820
Method and system for approximating distributed constant line Mar 1, 2000 Issued
Array ( [id] => 1432013 [patent_doc_number] => 06516448 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Fiber aligning structure' [patent_app_type] => B1 [patent_app_number] => 09/506743 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1354 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516448.pdf [firstpage_image] =>[orig_patent_app_number] => 09506743 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/506743
Fiber aligning structure Feb 17, 2000 Issued
Array ( [id] => 1460243 [patent_doc_number] => 06463566 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Dynamic double sampling charge integrator' [patent_app_type] => B1 [patent_app_number] => 09/497985 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 44 [patent_no_of_words] => 5988 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463566.pdf [firstpage_image] =>[orig_patent_app_number] => 09497985 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497985
Dynamic double sampling charge integrator Feb 3, 2000 Issued
Array ( [id] => 1460239 [patent_doc_number] => 06463565 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method for designing object-oriented table driven state machines' [patent_app_type] => B1 [patent_app_number] => 09/477435 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4218 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463565.pdf [firstpage_image] =>[orig_patent_app_number] => 09477435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477435
Method for designing object-oriented table driven state machines Jan 3, 2000 Issued
Array ( [id] => 4280476 [patent_doc_number] => 06323699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method and apparatus for variably providing an input signal' [patent_app_type] => 1 [patent_app_number] => 9/474829 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3497 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323699.pdf [firstpage_image] =>[orig_patent_app_number] => 474829 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474829
Method and apparatus for variably providing an input signal Dec 29, 1999 Issued
Array ( [id] => 7635860 [patent_doc_number] => 06380800 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Pump area reduction through the use of passive RC-filters or active filters' [patent_app_type] => B1 [patent_app_number] => 09/475164 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 4844 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380800.pdf [firstpage_image] =>[orig_patent_app_number] => 09475164 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475164
Pump area reduction through the use of passive RC-filters or active filters Dec 29, 1999 Issued
Array ( [id] => 1548308 [patent_doc_number] => 06445233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Multiple time constant rectifier apparatus and method' [patent_app_type] => B1 [patent_app_number] => 09/475802 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6594 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445233.pdf [firstpage_image] =>[orig_patent_app_number] => 09475802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475802
Multiple time constant rectifier apparatus and method Dec 29, 1999 Issued
Array ( [id] => 1563716 [patent_doc_number] => 06362666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Precision and fast recovery buffer' [patent_app_type] => B1 [patent_app_number] => 09/475102 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3679 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362666.pdf [firstpage_image] =>[orig_patent_app_number] => 09475102 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475102
Precision and fast recovery buffer Dec 29, 1999 Issued
Array ( [id] => 1312053 [patent_doc_number] => 06625800 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Method and apparatus for physical image based inspection system' [patent_app_type] => B1 [patent_app_number] => 09/476318 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4771 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625800.pdf [firstpage_image] =>[orig_patent_app_number] => 09476318 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476318
Method and apparatus for physical image based inspection system Dec 29, 1999 Issued
Array ( [id] => 1170721 [patent_doc_number] => 06766502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Method and apparatus for routing using deferred merging' [patent_app_type] => B1 [patent_app_number] => 09/476416 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4940 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766502.pdf [firstpage_image] =>[orig_patent_app_number] => 09476416 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/476416
Method and apparatus for routing using deferred merging Dec 29, 1999 Issued
Array ( [id] => 6998762 [patent_doc_number] => 20010052802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'MATCHED CURRENT DIFFERENTIAL AMPLIFIER' [patent_app_type] => new [patent_app_number] => 09/475261 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3134 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20010052802.pdf [firstpage_image] =>[orig_patent_app_number] => 09475261 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475261
Matched current differential amplifier Dec 29, 1999 Issued
Array ( [id] => 4296469 [patent_doc_number] => 06211707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Output buffer circuit with preset function' [patent_app_type] => 1 [patent_app_number] => 9/474553 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3851 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211707.pdf [firstpage_image] =>[orig_patent_app_number] => 474553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474553
Output buffer circuit with preset function Dec 28, 1999 Issued
Array ( [id] => 1476840 [patent_doc_number] => 06388475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Voltage tolerant high drive pull-up driver for an I/O buffer' [patent_app_type] => B1 [patent_app_number] => 09/474566 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2382 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/388/06388475.pdf [firstpage_image] =>[orig_patent_app_number] => 09474566 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474566
Voltage tolerant high drive pull-up driver for an I/O buffer Dec 28, 1999 Issued
Array ( [id] => 1456975 [patent_doc_number] => 06457159 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Functional timing analysis for characterization of virtual component blocks' [patent_app_type] => B1 [patent_app_number] => 09/477710 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 10985 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457159.pdf [firstpage_image] =>[orig_patent_app_number] => 09477710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477710
Functional timing analysis for characterization of virtual component blocks Dec 27, 1999 Issued
Array ( [id] => 4304321 [patent_doc_number] => 06198344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Back bias voltage level sensing circuit' [patent_app_type] => 1 [patent_app_number] => 9/469309 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 4311 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198344.pdf [firstpage_image] =>[orig_patent_app_number] => 469309 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469309
Back bias voltage level sensing circuit Dec 21, 1999 Issued
Array ( [id] => 4268064 [patent_doc_number] => 06259284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Charge free power-on-reset circuit' [patent_app_type] => 1 [patent_app_number] => 9/470256 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1801 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259284.pdf [firstpage_image] =>[orig_patent_app_number] => 470256 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470256
Charge free power-on-reset circuit Dec 21, 1999 Issued
Array ( [id] => 4425305 [patent_doc_number] => 06225834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Bit line sense amplifier' [patent_app_type] => 1 [patent_app_number] => 9/468360 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2352 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225834.pdf [firstpage_image] =>[orig_patent_app_number] => 468360 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468360
Bit line sense amplifier Dec 20, 1999 Issued
Array ( [id] => 1513540 [patent_doc_number] => 06442744 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method and apparatus for improving auto-placement in semiconductor integrated circuit design' [patent_app_type] => B1 [patent_app_number] => 09/457734 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 3688 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442744.pdf [firstpage_image] =>[orig_patent_app_number] => 09457734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457734
Method and apparatus for improving auto-placement in semiconductor integrated circuit design Dec 9, 1999 Issued
Array ( [id] => 1525075 [patent_doc_number] => 06415423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'LSI design system' [patent_app_type] => B1 [patent_app_number] => 09/447807 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 6146 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415423.pdf [firstpage_image] =>[orig_patent_app_number] => 09447807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447807
LSI design system Nov 22, 1999 Issued
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