Paul Dinh

Array ( [id] => 4312659 [patent_doc_number] => 06252446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method and electrical circuit for regulating dead time given varying pulse repetition rates' [patent_app_type] => 1 [patent_app_number] => 9/367908 [patent_app_country] => US [patent_app_date] => 1999-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2085 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252446.pdf [firstpage_image] =>[orig_patent_app_number] => 367908 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431243 [patent_doc_number] => 06507938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Methods for improving the performance of VLSI layouts designed by a timing driven physical design tool' [patent_app_type] => B1 [patent_app_number] => 09/439877 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 6913 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507938.pdf [firstpage_image] =>[orig_patent_app_number] => 09439877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1432446 [patent_doc_number] => 06505338 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Computer readable medium with definition of interface recorded thereon, verification method for feasibility to connect given circuit and method of generating signal pattern' [patent_app_type] => B1 [patent_app_number] => 09/420485 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4682 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505338.pdf [firstpage_image] =>[orig_patent_app_number] => 09420485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1354141 [patent_doc_number] => 06594803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Method and apparatus that reports multiple status events with a single monitor' [patent_app_type] => B1 [patent_app_number] => 09/406016 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 8042 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594803.pdf [firstpage_image] =>[orig_patent_app_number] => 09406016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1525072 [patent_doc_number] => 06415422 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method and system for performing capacitance estimations on an integrated circuit design routed by a global routing tool' [patent_app_type] => B1 [patent_app_number] => 09/397762 [patent_app_country] => US [patent_app_date] => 1999-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3251 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415422.pdf [firstpage_image] =>[orig_patent_app_number] => 09397762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1430732 [patent_doc_number] => 06526544 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Directly verifying a black box system' [patent_app_type] => B1 [patent_app_number] => 09/396830 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7112 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526544.pdf [firstpage_image] =>[orig_patent_app_number] => 09396830 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1462201 [patent_doc_number] => 06392464 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Wide bandwidth circuits for high linearity optical modulators' [patent_app_type] => B1 [patent_app_number] => 09/395443 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1968 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392464.pdf [firstpage_image] =>[orig_patent_app_number] => 09395443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425317 [patent_doc_number] => 06225838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Integrated circuit buffers having reduced power consumption requirements' [patent_app_type] => 1 [patent_app_number] => 9/395650 [patent_app_country] => US [patent_app_date] => 1999-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2426 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225838.pdf [firstpage_image] =>[orig_patent_app_number] => 395650 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7063802 [patent_doc_number] => 20010043087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'SENSE AMPLIFYING CIRCUIT' [patent_app_type] => new [patent_app_number] => 09/393779 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3958 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20010043087.pdf [firstpage_image] =>[orig_patent_app_number] => 09393779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4392051 [patent_doc_number] => 06262609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Closed-loop voltage-to-frequency converter' [patent_app_type] => 1 [patent_app_number] => 9/394188 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3690 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262609.pdf [firstpage_image] =>[orig_patent_app_number] => 394188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1436974 [patent_doc_number] => 06356120 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Electronic circuit configuration' [patent_app_type] => B1 [patent_app_number] => 09/394196 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1709 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356120.pdf [firstpage_image] =>[orig_patent_app_number] => 09394196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4414532 [patent_doc_number] => 06239631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Integrated circuit device with input buffer capable of correspondence with highspeed clock' [patent_app_type] => 1 [patent_app_number] => 9/377104 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5254 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239631.pdf [firstpage_image] =>[orig_patent_app_number] => 377104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4336735 [patent_doc_number] => 06320443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'RC delay time stabilizing circuit' [patent_app_type] => 1 [patent_app_number] => 9/377165 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1775 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320443.pdf [firstpage_image] =>[orig_patent_app_number] => 377165 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4326664 [patent_doc_number] => 06249160 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Clock reproduction and identification apparatus' [patent_app_type] => 1 [patent_app_number] => 9/376496 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 8501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249160.pdf [firstpage_image] =>[orig_patent_app_number] => 376496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1382981 [patent_doc_number] => 06574787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'Method and apparatus for logic synthesis (word oriented netlist)' [patent_app_type] => B1 [patent_app_number] => 09/375836 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 50 [patent_no_of_words] => 19945 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/574/06574787.pdf [firstpage_image] =>[orig_patent_app_number] => 09375836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4303686 [patent_doc_number] => 06184732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Setting the common mode level of a differential charge pump output' [patent_app_type] => 1 [patent_app_number] => 9/370622 [patent_app_country] => US [patent_app_date] => 1999-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3344 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184732.pdf [firstpage_image] =>[orig_patent_app_number] => 370622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1424112 [patent_doc_number] => 06518801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Alias suppression method for 1-bit precision direct digital synthesizer' [patent_app_type] => B1 [patent_app_number] => 09/368172 [patent_app_country] => US [patent_app_date] => 1999-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 2573 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518801.pdf [firstpage_image] =>[orig_patent_app_number] => 09368172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4365377 [patent_doc_number] => 06169433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method and apparatus using feedback to generate a ramped voltage with controlled maximum amplitude' [patent_app_type] => 1 [patent_app_number] => 9/365968 [patent_app_country] => US [patent_app_date] => 1999-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2995 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169433.pdf [firstpage_image] =>[orig_patent_app_number] => 365968 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1469060 [patent_doc_number] => 06459306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Low power differential comparator with stable hysteresis' [patent_app_type] => B1 [patent_app_number] => 09/358558 [patent_app_country] => US [patent_app_date] => 1999-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2481 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459306.pdf [firstpage_image] =>[orig_patent_app_number] => 09358558 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4303794 [patent_doc_number] => 06184740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Control Circuit' [patent_app_type] => 1 [patent_app_number] => 9/357240 [patent_app_country] => US [patent_app_date] => 1999-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2286 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184740.pdf [firstpage_image] =>[orig_patent_app_number] => 357240 [rel_patent_id] =>[rel_patent_doc_number] =>)