Search

Paul Dinh

Examiner (ID: 13722, Phone: (571)272-1890 , Office: P/2851 )

Most Active Art Unit
2851
Art Unit(s)
2851, 2816, 2825
Total Applications
2030
Issued Applications
1783
Pending Applications
89
Abandoned Applications
177

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4416159 [patent_doc_number] => 06265928 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Precision-controlled logarithmic amplifier' [patent_app_type] => 1 [patent_app_number] => 9/354984 [patent_app_country] => US [patent_app_date] => 1999-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3108 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265928.pdf [firstpage_image] =>[orig_patent_app_number] => 354984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354984
Precision-controlled logarithmic amplifier Jul 15, 1999 Issued
09/354461 CAPACITOR-BASED EXPONENTIAL PROGRAMMABLE GAIN AMPLIFIER Jul 14, 1999 Abandoned
Array ( [id] => 4412883 [patent_doc_number] => 06232817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Temperature stabilization of a predistorter with voltage supply' [patent_app_type] => 1 [patent_app_number] => 9/352792 [patent_app_country] => US [patent_app_date] => 1999-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2179 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232817.pdf [firstpage_image] =>[orig_patent_app_number] => 352792 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/352792
Temperature stabilization of a predistorter with voltage supply Jul 13, 1999 Issued
Array ( [id] => 1431220 [patent_doc_number] => 06507933 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Automatic defect source classification' [patent_app_type] => B1 [patent_app_number] => 09/351540 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6956 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507933.pdf [firstpage_image] =>[orig_patent_app_number] => 09351540 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351540
Automatic defect source classification Jul 11, 1999 Issued
Array ( [id] => 4245022 [patent_doc_number] => 06144233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Gain control circuit for controlling operation of a variable-gain amplifier or the like' [patent_app_type] => 1 [patent_app_number] => 9/350916 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6005 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144233.pdf [firstpage_image] =>[orig_patent_app_number] => 350916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/350916
Gain control circuit for controlling operation of a variable-gain amplifier or the like Jul 11, 1999 Issued
Array ( [id] => 1452935 [patent_doc_number] => 06456121 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-24 [patent_title] => 'Sense amplifier for integrated circuits using PMOS transistors' [patent_app_type] => B2 [patent_app_number] => 09/351141 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1487 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/456/06456121.pdf [firstpage_image] =>[orig_patent_app_number] => 09351141 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351141
Sense amplifier for integrated circuits using PMOS transistors Jul 11, 1999 Issued
Array ( [id] => 4267232 [patent_doc_number] => 06204698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Robust low voltage swing sense amplifier' [patent_app_type] => 1 [patent_app_number] => 9/351144 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3052 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204698.pdf [firstpage_image] =>[orig_patent_app_number] => 351144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351144
Robust low voltage swing sense amplifier Jul 11, 1999 Issued
Array ( [id] => 4368584 [patent_doc_number] => 06255861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Hybrid low voltage swing sense amplifier' [patent_app_type] => 1 [patent_app_number] => 9/351140 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3809 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255861.pdf [firstpage_image] =>[orig_patent_app_number] => 351140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351140
Hybrid low voltage swing sense amplifier Jul 11, 1999 Issued
Array ( [id] => 4358075 [patent_doc_number] => 06215341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Deceleration circuit' [patent_app_type] => 1 [patent_app_number] => 9/351096 [patent_app_country] => US [patent_app_date] => 1999-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1618 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215341.pdf [firstpage_image] =>[orig_patent_app_number] => 351096 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351096
Deceleration circuit Jul 8, 1999 Issued
Array ( [id] => 1309429 [patent_doc_number] => 06629295 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Design automation method and device' [patent_app_type] => B1 [patent_app_number] => 09/339117 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4765 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629295.pdf [firstpage_image] =>[orig_patent_app_number] => 09339117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/339117
Design automation method and device Jun 23, 1999 Issued
Array ( [id] => 4326799 [patent_doc_number] => 06249167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Semiconductor integrated circuit, semiconductor device, and electronic equipment comprising the same' [patent_app_type] => 1 [patent_app_number] => 9/254136 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 12 [patent_no_of_words] => 13751 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249167.pdf [firstpage_image] =>[orig_patent_app_number] => 254136 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/254136
Semiconductor integrated circuit, semiconductor device, and electronic equipment comprising the same Jun 2, 1999 Issued
Array ( [id] => 4277741 [patent_doc_number] => 06307412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Clock monitor circuit and synchronous semiconductor memory device utilizing the circuit' [patent_app_type] => 1 [patent_app_number] => 9/323590 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3770 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/307/06307412.pdf [firstpage_image] =>[orig_patent_app_number] => 323590 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323590
Clock monitor circuit and synchronous semiconductor memory device utilizing the circuit May 31, 1999 Issued
Array ( [id] => 4392262 [patent_doc_number] => 06262623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Log-domain filter having a variable dynamic range window' [patent_app_type] => 1 [patent_app_number] => 9/322401 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7520 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262623.pdf [firstpage_image] =>[orig_patent_app_number] => 322401 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322401
Log-domain filter having a variable dynamic range window May 27, 1999 Issued
Array ( [id] => 7639599 [patent_doc_number] => 06396317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Digital voltage controlled oscillator' [patent_app_type] => B1 [patent_app_number] => 09/323185 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5321 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396317.pdf [firstpage_image] =>[orig_patent_app_number] => 09323185 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323185
Digital voltage controlled oscillator May 27, 1999 Issued
Array ( [id] => 4255882 [patent_doc_number] => 06137328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Clock phase correction circuit' [patent_app_type] => 1 [patent_app_number] => 9/321888 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4793 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137328.pdf [firstpage_image] =>[orig_patent_app_number] => 321888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/321888
Clock phase correction circuit May 27, 1999 Issued
Array ( [id] => 4267328 [patent_doc_number] => 06204705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Delay locked loop for sub-micron single-poly digital CMOS processes' [patent_app_type] => 1 [patent_app_number] => 9/322668 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 7354 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204705.pdf [firstpage_image] =>[orig_patent_app_number] => 322668 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322668
Delay locked loop for sub-micron single-poly digital CMOS processes May 27, 1999 Issued
Array ( [id] => 4413441 [patent_doc_number] => 06172539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Synchronous buffer circuit and data transmission circuit having the synchronous buffer circuit' [patent_app_type] => 1 [patent_app_number] => 9/322216 [patent_app_country] => US [patent_app_date] => 1999-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3606 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172539.pdf [firstpage_image] =>[orig_patent_app_number] => 322216 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322216
Synchronous buffer circuit and data transmission circuit having the synchronous buffer circuit May 27, 1999 Issued
Array ( [id] => 4423968 [patent_doc_number] => 06194930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'DLL circuit' [patent_app_type] => 1 [patent_app_number] => 9/320847 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11644 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194930.pdf [firstpage_image] =>[orig_patent_app_number] => 320847 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/320847
DLL circuit May 25, 1999 Issued
Array ( [id] => 1501763 [patent_doc_number] => 06405344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method for performing design trade-off' [patent_app_type] => B1 [patent_app_number] => 09/312688 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2335 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405344.pdf [firstpage_image] =>[orig_patent_app_number] => 09312688 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/312688
Method for performing design trade-off May 13, 1999 Issued
Array ( [id] => 1331810 [patent_doc_number] => 06600356 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'ESD protection circuit with controlled breakdown voltage' [patent_app_type] => B1 [patent_app_number] => 09/302562 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2653 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/600/06600356.pdf [firstpage_image] =>[orig_patent_app_number] => 09302562 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302562
ESD protection circuit with controlled breakdown voltage Apr 29, 1999 Issued
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