Search

Paul E. Patton

Examiner (ID: 3173, Phone: (571)272-9762 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2112, 2822, 2809
Total Applications
977
Issued Applications
886
Pending Applications
1
Abandoned Applications
94

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11246348 [patent_doc_number] => 09472395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Semiconductor arrangement including buried anodic oxide and manufacturing method' [patent_app_type] => utility [patent_app_number] => 14/594838 [patent_app_country] => US [patent_app_date] => 2015-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5247 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14594838 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/594838
Semiconductor arrangement including buried anodic oxide and manufacturing method Jan 11, 2015 Issued
Array ( [id] => 10642339 [patent_doc_number] => 09359192 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-07 [patent_title] => 'Microelectromechanical systems (MEMS) devices with control circuits and methods of fabrication' [patent_app_type] => utility [patent_app_number] => 14/593582 [patent_app_country] => US [patent_app_date] => 2015-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6249 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14593582 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/593582
Microelectromechanical systems (MEMS) devices with control circuits and methods of fabrication Jan 8, 2015 Issued
Array ( [id] => 11239985 [patent_doc_number] => 09466632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-11 [patent_title] => 'Image sensor package and an image sensor module having the same' [patent_app_type] => utility [patent_app_number] => 14/593500 [patent_app_country] => US [patent_app_date] => 2015-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 9413 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14593500 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/593500
Image sensor package and an image sensor module having the same Jan 8, 2015 Issued
Array ( [id] => 10604274 [patent_doc_number] => 09324846 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-26 [patent_title] => 'Field plate in heterojunction bipolar transistor with improved break-down voltage' [patent_app_type] => utility [patent_app_number] => 14/591946 [patent_app_country] => US [patent_app_date] => 2015-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 6218 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14591946 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/591946
Field plate in heterojunction bipolar transistor with improved break-down voltage Jan 7, 2015 Issued
Array ( [id] => 10544526 [patent_doc_number] => 09269659 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-23 [patent_title] => 'Interposer with overmolded vias' [patent_app_type] => utility [patent_app_number] => 14/591934 [patent_app_country] => US [patent_app_date] => 2015-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2504 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14591934 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/591934
Interposer with overmolded vias Jan 7, 2015 Issued
Array ( [id] => 11007300 [patent_doc_number] => 20160204253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'III-V MOSFET WITH STRAINED CHANNEL AND SEMI-INSULATING BOTTOM BARRIER' [patent_app_type] => utility [patent_app_number] => 14/592130 [patent_app_country] => US [patent_app_date] => 2015-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5185 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14592130 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/592130
III-V MOSFET with strained channel and semi-insulating bottom barrier Jan 7, 2015 Issued
Array ( [id] => 11221702 [patent_doc_number] => 09450046 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Semiconductor structure with fin structure and wire structure and method for forming the same' [patent_app_type] => utility [patent_app_number] => 14/592089 [patent_app_country] => US [patent_app_date] => 2015-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 7499 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14592089 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/592089
Semiconductor structure with fin structure and wire structure and method for forming the same Jan 7, 2015 Issued
Array ( [id] => 10638438 [patent_doc_number] => 09355950 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-31 [patent_title] => 'Power semiconductor module having low gate drive inductance flexible board connection' [patent_app_type] => utility [patent_app_number] => 14/592244 [patent_app_country] => US [patent_app_date] => 2015-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8280 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14592244 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/592244
Power semiconductor module having low gate drive inductance flexible board connection Jan 7, 2015 Issued
Array ( [id] => 10780247 [patent_doc_number] => 20160126403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'OPTICAL MODULE PACKAGE AND ITS PACKAGING METHOD' [patent_app_type] => utility [patent_app_number] => 14/590807 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2738 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590807 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/590807
Optical module package and its packaging method Jan 5, 2015 Issued
Array ( [id] => 10583743 [patent_doc_number] => 09305869 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-05 [patent_title] => 'Packaged semiconductor device having leadframe features as pressure valves against delamination' [patent_app_type] => utility [patent_app_number] => 14/587629 [patent_app_country] => US [patent_app_date] => 2014-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3246 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14587629 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/587629
Packaged semiconductor device having leadframe features as pressure valves against delamination Dec 30, 2014 Issued
Array ( [id] => 10993247 [patent_doc_number] => 20160190194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'PHOTODETECTOR FOCAL PLANE ARRAY SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 14/587068 [patent_app_country] => US [patent_app_date] => 2014-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5502 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14587068 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/587068
Photodetector focal plane array systems and methods Dec 30, 2014 Issued
Array ( [id] => 13695381 [patent_doc_number] => 20170358645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => HIGH MOBILITY NANOWIRE FIN CHANNEL ON SILICON SUBSTRATE FORMED USING SACRIFICIAL SUB-FIN [patent_app_type] => utility [patent_app_number] => 15/525269 [patent_app_country] => US [patent_app_date] => 2014-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24064 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15525269 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/525269
High mobility nanowire fin channel on silicon substrate formed using sacrificial sub-fin Dec 25, 2014 Issued
Array ( [id] => 10259884 [patent_doc_number] => 20150144880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'NON-PLANAR GATE ALL-AROUND DEVICE AND METHOD OF FABRICATION THEREOF' [patent_app_type] => utility [patent_app_number] => 14/582131 [patent_app_country] => US [patent_app_date] => 2014-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11204 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14582131 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/582131
Non-planar gate all-around device and method of fabrication thereof Dec 22, 2014 Issued
Array ( [id] => 10262027 [patent_doc_number] => 20150147024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'Sacrificial Waveguide Test Structures' [patent_app_type] => utility [patent_app_number] => 14/564078 [patent_app_country] => US [patent_app_date] => 2014-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4484 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14564078 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/564078
Sacrificial waveguide test structures Dec 7, 2014 Issued
Array ( [id] => 11194360 [patent_doc_number] => 09425180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Treating copper surfaces for packaging' [patent_app_type] => utility [patent_app_number] => 14/550337 [patent_app_country] => US [patent_app_date] => 2014-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3219 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14550337 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/550337
Treating copper surfaces for packaging Nov 20, 2014 Issued
Array ( [id] => 9917282 [patent_doc_number] => 20150072487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'Semiconductor Device and Method of Forming the Same' [patent_app_type] => utility [patent_app_number] => 14/547068 [patent_app_country] => US [patent_app_date] => 2014-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5441 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14547068 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/547068
Semiconductor device and method of forming the same Nov 17, 2014 Issued
Array ( [id] => 10765345 [patent_doc_number] => 20160111501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'METHOD TO DEFINE THE ACTIVE REGION OF A TRANSISTOR EMPLOYING A GROUP III-V SEMICONDUCTOR MATERIAL' [patent_app_type] => utility [patent_app_number] => 14/516696 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6111 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14516696 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/516696
Method to define the active region of a transistor employing a group III-V semiconductor material Oct 16, 2014 Issued
Array ( [id] => 10495631 [patent_doc_number] => 20150380653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'Electro-Luminescence Display Panel and Fabrication Method Thereof, Display Device' [patent_app_type] => utility [patent_app_number] => 14/516703 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3643 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14516703 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/516703
Electro-luminescence display panel and fabrication method thereof, display device Oct 16, 2014 Issued
Array ( [id] => 10544602 [patent_doc_number] => 09269737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-23 [patent_title] => 'Flat panel image sensor and method of manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 14/516982 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 3457 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14516982 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/516982
Flat panel image sensor and method of manufacturing thereof Oct 16, 2014 Issued
Array ( [id] => 11782002 [patent_doc_number] => 09391208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Electronic device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/517065 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 52 [patent_no_of_words] => 7257 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517065 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/517065
Electronic device and method of manufacturing the same Oct 16, 2014 Issued
Menu