
Paul E. Patton
Examiner (ID: 3173, Phone: (571)272-9762 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2112, 2822, 2809 |
| Total Applications | 977 |
| Issued Applications | 886 |
| Pending Applications | 1 |
| Abandoned Applications | 94 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10019425
[patent_doc_number] => 09061896
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-06-23
[patent_title] => 'Method for manufacturing a MEMS device and MEMS device'
[patent_app_type] => utility
[patent_app_number] => 14/010360
[patent_app_country] => US
[patent_app_date] => 2013-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 4832
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 28
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14010360
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/010360 | Method for manufacturing a MEMS device and MEMS device | Aug 25, 2013 | Issued |
Array
(
[id] => 9965347
[patent_doc_number] => 09012964
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-21
[patent_title] => 'Modulating germanium percentage in MOS devices'
[patent_app_type] => utility
[patent_app_number] => 13/963855
[patent_app_country] => US
[patent_app_date] => 2013-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 4039
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963855
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/963855 | Modulating germanium percentage in MOS devices | Aug 8, 2013 | Issued |
Array
(
[id] => 9964704
[patent_doc_number] => 09012315
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-21
[patent_title] => 'Methods and systems for dopant activation using microwave radiation'
[patent_app_type] => utility
[patent_app_number] => 13/963043
[patent_app_country] => US
[patent_app_date] => 2013-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2821
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963043
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/963043 | Methods and systems for dopant activation using microwave radiation | Aug 8, 2013 | Issued |
Array
(
[id] => 10022530
[patent_doc_number] => 09065026
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-06-23
[patent_title] => 'Lens element for distributing light with a uniform intensity distribution and lighting device comprised thereof'
[patent_app_type] => utility
[patent_app_number] => 13/960916
[patent_app_country] => US
[patent_app_date] => 2013-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4028
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13960916
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/960916 | Lens element for distributing light with a uniform intensity distribution and lighting device comprised thereof | Aug 6, 2013 | Issued |
Array
(
[id] => 10876922
[patent_doc_number] => 08901711
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-12-02
[patent_title] => 'Horizontal metal-insulator-metal capacitor'
[patent_app_type] => utility
[patent_app_number] => 13/961553
[patent_app_country] => US
[patent_app_date] => 2013-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 6419
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13961553
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/961553 | Horizontal metal-insulator-metal capacitor | Aug 6, 2013 | Issued |
Array
(
[id] => 9861838
[patent_doc_number] => 20150041855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/960816
[patent_app_country] => US
[patent_app_date] => 2013-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4724
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13960816
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/960816 | Semiconductor device | Aug 6, 2013 | Issued |
Array
(
[id] => 10863804
[patent_doc_number] => 08889500
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-11-18
[patent_title] => 'Methods of forming stressed fin channel structures for FinFET semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 13/960244
[patent_app_country] => US
[patent_app_date] => 2013-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 9518
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13960244
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/960244 | Methods of forming stressed fin channel structures for FinFET semiconductor devices | Aug 5, 2013 | Issued |
Array
(
[id] => 10004167
[patent_doc_number] => 09048266
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-06-02
[patent_title] => 'Apparatus and methods for improving parallel conduction in a quantum well device'
[patent_app_type] => utility
[patent_app_number] => 13/956685
[patent_app_country] => US
[patent_app_date] => 2013-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4255
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13956685
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/956685 | Apparatus and methods for improving parallel conduction in a quantum well device | Jul 31, 2013 | Issued |
Array
(
[id] => 9990261
[patent_doc_number] => 09035468
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-05-19
[patent_title] => 'Copper post structure for wafer level chip scale package'
[patent_app_type] => utility
[patent_app_number] => 13/954046
[patent_app_country] => US
[patent_app_date] => 2013-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 3895
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13954046
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/954046 | Copper post structure for wafer level chip scale package | Jul 29, 2013 | Issued |
Array
(
[id] => 10118652
[patent_doc_number] => 09153540
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-06
[patent_title] => 'Semiconductor die connection system and method'
[patent_app_type] => utility
[patent_app_number] => 13/947953
[patent_app_country] => US
[patent_app_date] => 2013-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 6861
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13947953
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/947953 | Semiconductor die connection system and method | Jul 21, 2013 | Issued |
Array
(
[id] => 10035486
[patent_doc_number] => 09076812
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-07
[patent_title] => 'HEMT structure with iron-doping-stop component and methods of forming'
[patent_app_type] => utility
[patent_app_number] => 13/929161
[patent_app_country] => US
[patent_app_date] => 2013-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 3740
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13929161
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/929161 | HEMT structure with iron-doping-stop component and methods of forming | Jun 26, 2013 | Issued |
Array
(
[id] => 9121473
[patent_doc_number] => 20130288395
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-31
[patent_title] => 'MAGNETIC TUNNEL JUNCTION DEVICE FABRICATION'
[patent_app_type] => utility
[patent_app_number] => 13/925953
[patent_app_country] => US
[patent_app_date] => 2013-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7468
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13925953
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/925953 | Magnetic tunnel junction device fabrication | Jun 24, 2013 | Issued |
Array
(
[id] => 9762170
[patent_doc_number] => 08846491
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-09-30
[patent_title] => 'Forming a diffusion break during a RMG process'
[patent_app_type] => utility
[patent_app_number] => 13/921377
[patent_app_country] => US
[patent_app_date] => 2013-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 3730
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13921377
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/921377 | Forming a diffusion break during a RMG process | Jun 18, 2013 | Issued |
Array
(
[id] => 9534350
[patent_doc_number] => 20140158997
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-12
[patent_title] => 'DUAL-MODE PIXEL INCLUDING EMISSIVE AND REFLECTIVE DEVICES AND DUAL-MODE DISPLAY WITH THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/920134
[patent_app_country] => US
[patent_app_date] => 2013-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6389
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13920134
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/920134 | Dual-mode pixel including emissive and reflective devices and dual-mode display with the same | Jun 17, 2013 | Issued |
Array
(
[id] => 10964815
[patent_doc_number] => 20140367848
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-18
[patent_title] => 'Semiconductor Device and Method of Making an Embedded Wafer Level Ball Grid Array (EWLB) Package on Package (POP) Device With a Slotted Metal Carrier Interposer'
[patent_app_type] => utility
[patent_app_number] => 13/918103
[patent_app_country] => US
[patent_app_date] => 2013-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 8197
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13918103
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/918103 | Semiconductor device and method of making an embedded wafer level ball grid array (EWLB) package on package (POP) device with a slotted metal carrier interposer | Jun 13, 2013 | Issued |
Array
(
[id] => 10964815
[patent_doc_number] => 20140367848
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-18
[patent_title] => 'Semiconductor Device and Method of Making an Embedded Wafer Level Ball Grid Array (EWLB) Package on Package (POP) Device With a Slotted Metal Carrier Interposer'
[patent_app_type] => utility
[patent_app_number] => 13/918103
[patent_app_country] => US
[patent_app_date] => 2013-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 8197
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13918103
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/918103 | Semiconductor device and method of making an embedded wafer level ball grid array (EWLB) package on package (POP) device with a slotted metal carrier interposer | Jun 13, 2013 | Issued |
Array
(
[id] => 9104626
[patent_doc_number] => 20130277757
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-24
[patent_title] => 'Voids in STI Regions for Forming Bulk FinFETs'
[patent_app_type] => utility
[patent_app_number] => 13/918728
[patent_app_country] => US
[patent_app_date] => 2013-06-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2510
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13918728
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/918728 | Voids in STI regions for forming bulk FinFETs | Jun 13, 2013 | Issued |
Array
(
[id] => 9648511
[patent_doc_number] => 08802521
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-08-12
[patent_title] => 'Semiconductor fin-shaped structure and manufacturing process thereof'
[patent_app_type] => utility
[patent_app_number] => 13/909101
[patent_app_country] => US
[patent_app_date] => 2013-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 3590
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13909101
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/909101 | Semiconductor fin-shaped structure and manufacturing process thereof | Jun 3, 2013 | Issued |
Array
(
[id] => 10950821
[patent_doc_number] => 20140353842
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-04
[patent_title] => 'WIDE PIN FOR IMPROVED CIRCUIT ROUTING'
[patent_app_type] => utility
[patent_app_number] => 13/908096
[patent_app_country] => US
[patent_app_date] => 2013-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4330
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13908096
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/908096 | Wide pin for improved circuit routing | Jun 2, 2013 | Issued |
Array
(
[id] => 9763080
[patent_doc_number] => 08847409
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-09-30
[patent_title] => 'Compliant micro-socket hybridization method'
[patent_app_type] => utility
[patent_app_number] => 13/908409
[patent_app_country] => US
[patent_app_date] => 2013-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 10
[patent_no_of_words] => 2686
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13908409
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/908409 | Compliant micro-socket hybridization method | Jun 2, 2013 | Issued |