Search

Paul E. Patton

Examiner (ID: 359, Phone: (571)272-9762 , Office: P/2822 )

Most Active Art Unit
2822
Art Unit(s)
2809, 2112, 2822
Total Applications
977
Issued Applications
886
Pending Applications
1
Abandoned Applications
94

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9938015 [patent_doc_number] => 08987827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Prevention of faceting in epitaxial source drain transistors' [patent_app_type] => utility [patent_app_number] => 13/907690 [patent_app_country] => US [patent_app_date] => 2013-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 6060 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13907690 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/907690
Prevention of faceting in epitaxial source drain transistors May 30, 2013 Issued
Array ( [id] => 9171548 [patent_doc_number] => 20130313533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'Organic Light Emitting Diode Illuminating Device' [patent_app_type] => utility [patent_app_number] => 13/898606 [patent_app_country] => US [patent_app_date] => 2013-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3313 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13898606 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/898606
Organic light emitting diode illuminating device May 20, 2013 Issued
Array ( [id] => 9875972 [patent_doc_number] => 08963244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Semiconductor device, integrated circuit and method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/894751 [patent_app_country] => US [patent_app_date] => 2013-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6309 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894751 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/894751
Semiconductor device, integrated circuit and method of manufacturing a semiconductor device May 14, 2013 Issued
Array ( [id] => 10936674 [patent_doc_number] => 20140339694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'Semiconductor Devices Having a Glass Substrate, and Method for Manufacturing Thereof' [patent_app_type] => utility [patent_app_number] => 13/894682 [patent_app_country] => US [patent_app_date] => 2013-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8491 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13894682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/894682
Semiconductor devices having a glass substrate, and method for manufacturing thereof May 14, 2013 Issued
Array ( [id] => 10936624 [patent_doc_number] => 20140339645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'METHODS OF FORMING SEMICONDUCTOR DEVICES WITH DIFFERENT INSULATION THICKNESSES ON THE SAME SEMICONDUCTOR SUBSTRATE AND THE RESULTING DEVICES' [patent_app_type] => utility [patent_app_number] => 13/893955 [patent_app_country] => US [patent_app_date] => 2013-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5920 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893955 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/893955
Methods of forming semiconductor devices with different insulation thickness on the same semiconductor substrate and the resulting devices May 13, 2013 Issued
Array ( [id] => 10936611 [patent_doc_number] => 20140339632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/893635 [patent_app_country] => US [patent_app_date] => 2013-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893635 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/893635
Semiconductor structure and method for manufacturing the same May 13, 2013 Issued
Array ( [id] => 9051215 [patent_doc_number] => 20130248929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'Reducing Source/Drain Resistance of III-V Based Transistors' [patent_app_type] => utility [patent_app_number] => 13/873767 [patent_app_country] => US [patent_app_date] => 2013-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13873767 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/873767
Reducing source/drain resistance of III-V based transistors Apr 29, 2013 Issued
Array ( [id] => 9893311 [patent_doc_number] => 20150048510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/383915 [patent_app_country] => US [patent_app_date] => 2013-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5721 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14383915 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/383915
SEMICONDUCTOR DEVICE Apr 21, 2013 Abandoned
Array ( [id] => 10230249 [patent_doc_number] => 20150115243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-30 [patent_title] => 'SOLID-STATE IMAGE PICKUP DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/395401 [patent_app_country] => US [patent_app_date] => 2013-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8351 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14395401 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/395401
Solid-state image pickup device, method of manufacturing the same, and electronic apparatus Apr 16, 2013 Issued
Array ( [id] => 9428162 [patent_doc_number] => 08704240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'Light emitting devices having current reducing structures' [patent_app_type] => utility [patent_app_number] => 13/856928 [patent_app_country] => US [patent_app_date] => 2013-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 10655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13856928 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/856928
Light emitting devices having current reducing structures Apr 3, 2013 Issued
Array ( [id] => 8987026 [patent_doc_number] => 20130214307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/852015 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 15956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13852015 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/852015
Light emitting device Mar 27, 2013 Issued
Array ( [id] => 9662172 [patent_doc_number] => 08809147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-19 [patent_title] => 'Dual conducting floating spacer metal oxide semiconductor field effect transistor (DCFS MOSFET) and method to fabricate the same' [patent_app_type] => utility [patent_app_number] => 13/846571 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 3777 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13846571 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/846571
Dual conducting floating spacer metal oxide semiconductor field effect transistor (DCFS MOSFET) and method to fabricate the same Mar 17, 2013 Issued
Array ( [id] => 10016134 [patent_doc_number] => 09059155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-16 [patent_title] => 'Chip package and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 13/803108 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8800 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13803108 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/803108
Chip package and method for manufacturing the same Mar 13, 2013 Issued
Array ( [id] => 9978106 [patent_doc_number] => 09024418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-05 [patent_title] => 'Local interconnect structures for high density' [patent_app_type] => utility [patent_app_number] => 13/829864 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13829864 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/829864
Local interconnect structures for high density Mar 13, 2013 Issued
Array ( [id] => 9729125 [patent_doc_number] => 20140264832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'CHIP ARRANGEMENTS' [patent_app_type] => utility [patent_app_number] => 13/802848 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 20417 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13802848 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/802848
Chip arrangements Mar 13, 2013 Issued
Array ( [id] => 9682646 [patent_doc_number] => 20140239410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'Integrated Circuit with Standard Cells' [patent_app_type] => utility [patent_app_number] => 13/829484 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13829484 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/829484
Integrated circuit with standard cells Mar 13, 2013 Issued
Array ( [id] => 10831242 [patent_doc_number] => 08859410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-14 [patent_title] => 'Gate stack of boron semiconductor alloy, polysilicon and high-k gate dielectric for low voltage applications' [patent_app_type] => utility [patent_app_number] => 13/828846 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 5920 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13828846 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/828846
Gate stack of boron semiconductor alloy, polysilicon and high-k gate dielectric for low voltage applications Mar 13, 2013 Issued
Array ( [id] => 9728813 [patent_doc_number] => 20140264520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR PROTECTION FROM DAMAGE TO GATE DIELECTRIC' [patent_app_type] => utility [patent_app_number] => 13/801928 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14252 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13801928 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/801928
Integrated circuit structure and method for protection from damage to gate dielectric Mar 12, 2013 Issued
Array ( [id] => 9850181 [patent_doc_number] => 08951909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Integrated circuit structure and formation' [patent_app_type] => utility [patent_app_number] => 13/801676 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13801676 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/801676
Integrated circuit structure and formation Mar 12, 2013 Issued
Array ( [id] => 9898710 [patent_doc_number] => 20150053908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'MEMRISTIVE DEVICE AND METHOD OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 14/384035 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15835 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14384035 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/384035
MEMRISTIVE DEVICE AND METHOD OF MANUFACTURE Mar 10, 2013 Abandoned
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