
Paul E. Patton
Examiner (ID: 3173, Phone: (571)272-9762 , Office: P/2822 )
| Most Active Art Unit | 2822 |
| Art Unit(s) | 2112, 2822, 2809 |
| Total Applications | 977 |
| Issued Applications | 886 |
| Pending Applications | 1 |
| Abandoned Applications | 94 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11411878
[patent_doc_number] => 09559194
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-31
[patent_title] => 'Transistors and methods of forming transistors'
[patent_app_type] => utility
[patent_app_number] => 15/003679
[patent_app_country] => US
[patent_app_date] => 2016-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 15
[patent_no_of_words] => 4047
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15003679
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/003679 | Transistors and methods of forming transistors | Jan 20, 2016 | Issued |
Array
(
[id] => 11240042
[patent_doc_number] => 09466690
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-10-11
[patent_title] => 'Precisely controlling III-V height'
[patent_app_type] => utility
[patent_app_number] => 14/994738
[patent_app_country] => US
[patent_app_date] => 2016-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 33
[patent_no_of_words] => 7240
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14994738
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/994738 | Precisely controlling III-V height | Jan 12, 2016 | Issued |
Array
(
[id] => 11007237
[patent_doc_number] => 20160204189
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-14
[patent_title] => 'METHOD AND APPARATUS FOR AN INTEGRATED CAPACITOR'
[patent_app_type] => utility
[patent_app_number] => 14/991078
[patent_app_country] => US
[patent_app_date] => 2016-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5604
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14991078
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/991078 | Method and apparatus for an integrated capacitor | Jan 7, 2016 | Issued |
Array
(
[id] => 11014262
[patent_doc_number] => 20160211215
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-21
[patent_title] => 'SEMICONDUCTOR DEVICES'
[patent_app_type] => utility
[patent_app_number] => 14/991020
[patent_app_country] => US
[patent_app_date] => 2016-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 10193
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14991020
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/991020 | Semiconductor devices | Jan 7, 2016 | Issued |
Array
(
[id] => 11483543
[patent_doc_number] => 09590103
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-03-07
[patent_title] => 'Semiconductor devices having multiple gate structures and methods of manufacturing such devices'
[patent_app_type] => utility
[patent_app_number] => 14/990863
[patent_app_country] => US
[patent_app_date] => 2016-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 21
[patent_no_of_words] => 12750
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990863
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/990863 | Semiconductor devices having multiple gate structures and methods of manufacturing such devices | Jan 7, 2016 | Issued |
Array
(
[id] => 11539450
[patent_doc_number] => 09613865
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-04
[patent_title] => 'Semiconductor die and die cutting method'
[patent_app_type] => utility
[patent_app_number] => 14/990830
[patent_app_country] => US
[patent_app_date] => 2016-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5517
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990830
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/990830 | Semiconductor die and die cutting method | Jan 7, 2016 | Issued |
Array
(
[id] => 11286557
[patent_doc_number] => 09502416
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-11-22
[patent_title] => 'Semiconductor device including transistors having different threshold voltages'
[patent_app_type] => utility
[patent_app_number] => 14/990992
[patent_app_country] => US
[patent_app_date] => 2016-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 11909
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990992
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/990992 | Semiconductor device including transistors having different threshold voltages | Jan 7, 2016 | Issued |
Array
(
[id] => 11599790
[patent_doc_number] => 09646967
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-09
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/990951
[patent_app_country] => US
[patent_app_date] => 2016-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 19
[patent_no_of_words] => 8984
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990951
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/990951 | Semiconductor device | Jan 7, 2016 | Issued |
Array
(
[id] => 11021086
[patent_doc_number] => 20160218041
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-28
[patent_title] => 'TECHNIQUE OF REDUCING SHALLOW TRENCH ISOLATION LOSS DURING FIN FORMATION IN FINFETS'
[patent_app_type] => utility
[patent_app_number] => 14/991184
[patent_app_country] => US
[patent_app_date] => 2016-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4134
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14991184
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/991184 | Technique of reducing shallow trench isolation loss during fin formation in finFETs | Jan 7, 2016 | Issued |
Array
(
[id] => 11466848
[patent_doc_number] => 09583489
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-02-28
[patent_title] => 'Solid state diffusion doping for bulk finFET devices'
[patent_app_type] => utility
[patent_app_number] => 14/991417
[patent_app_country] => US
[patent_app_date] => 2016-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 37
[patent_no_of_words] => 6205
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14991417
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/991417 | Solid state diffusion doping for bulk finFET devices | Jan 7, 2016 | Issued |
Array
(
[id] => 11014251
[patent_doc_number] => 20160211204
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-07-21
[patent_title] => 'ELECTRONIC PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 14/990887
[patent_app_country] => US
[patent_app_date] => 2016-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4026
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990887
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/990887 | Electronic package | Jan 7, 2016 | Issued |
Array
(
[id] => 11404896
[patent_doc_number] => 20170025434
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-26
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/991084
[patent_app_country] => US
[patent_app_date] => 2016-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7289
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14991084
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/991084 | Semiconductor memory device and method of manufacturing the same | Jan 7, 2016 | Issued |
Array
(
[id] => 10787536
[patent_doc_number] => 20160133692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-05-12
[patent_title] => 'UNIAXIALLY-STRAINED FD-SOI FINFET'
[patent_app_type] => utility
[patent_app_number] => 14/982474
[patent_app_country] => US
[patent_app_date] => 2015-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8968
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14982474
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/982474 | Uniaxially-strained FD-SOI finFET | Dec 28, 2015 | Issued |
Array
(
[id] => 10741087
[patent_doc_number] => 20160087238
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-24
[patent_title] => 'ORGANIC LIGHT-EMITTING DISPLAY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 14/962445
[patent_app_country] => US
[patent_app_date] => 2015-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 15501
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14962445
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/962445 | ORGANIC LIGHT-EMITTING DISPLAY APPARATUS | Dec 7, 2015 | Abandoned |
Array
(
[id] => 11187602
[patent_doc_number] => 09419013
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-08-16
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 14/956539
[patent_app_country] => US
[patent_app_date] => 2015-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 32
[patent_no_of_words] => 13307
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 55
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14956539
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/956539 | Semiconductor device and method of manufacturing the same | Dec 1, 2015 | Issued |
Array
(
[id] => 11259412
[patent_doc_number] => 09484317
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-11-01
[patent_title] => 'Scheme for connector site spacing and resulting structures'
[patent_app_type] => utility
[patent_app_number] => 14/942756
[patent_app_country] => US
[patent_app_date] => 2015-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 17
[patent_no_of_words] => 7455
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942756
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/942756 | Scheme for connector site spacing and resulting structures | Nov 15, 2015 | Issued |
Array
(
[id] => 11459991
[patent_doc_number] => 20170053897
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-02-23
[patent_title] => 'INDEPENDENT 3D STACKING'
[patent_app_type] => utility
[patent_app_number] => 14/935310
[patent_app_country] => US
[patent_app_date] => 2015-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 7693
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935310
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/935310 | Independent 3D stacking | Nov 5, 2015 | Issued |
Array
(
[id] => 11623308
[patent_doc_number] => 20170133496
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-05-11
[patent_title] => 'HIGH-ELECTRON-MOBILITY TRANSISTOR AND MANUFACTURING METHOD THEREOF'
[patent_app_type] => utility
[patent_app_number] => 14/935342
[patent_app_country] => US
[patent_app_date] => 2015-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 6527
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935342
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/935342 | High-electron-mobility transistor and manufacturing method thereof | Nov 5, 2015 | Issued |
Array
(
[id] => 11428900
[patent_doc_number] => 09567208
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-02-14
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 14/935318
[patent_app_country] => US
[patent_app_date] => 2015-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 35
[patent_no_of_words] => 9608
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935318
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/935318 | Semiconductor device and method for fabricating the same | Nov 5, 2015 | Issued |
Array
(
[id] => 11807282
[patent_doc_number] => 09548365
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-17
[patent_title] => 'Semiconductor device and method for manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/922524
[patent_app_country] => US
[patent_app_date] => 2015-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 22
[patent_no_of_words] => 7053
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14922524
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/922524 | Semiconductor device and method for manufacturing semiconductor device | Oct 25, 2015 | Issued |