Search

Paul J. Holland

Examiner (ID: 13306, Phone: (571)270-3537 , Office: P/1656 )

Most Active Art Unit
1656
Art Unit(s)
1656
Total Applications
946
Issued Applications
496
Pending Applications
113
Abandoned Applications
363

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18679910 [patent_doc_number] => 20230317568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => ISOLATION PACKAGE WITH HIGH THERMAL CONDUCTIVITY [patent_app_type] => utility [patent_app_number] => 17/710077 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4637 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710077 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/710077
ISOLATION PACKAGE WITH HIGH THERMAL CONDUCTIVITY Mar 30, 2022 Pending
Array ( [id] => 18950926 [patent_doc_number] => 11894232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Methods for forming charge layers using gas and liquid phase coatings [patent_app_type] => utility [patent_app_number] => 17/701242 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3811 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701242 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701242
Methods for forming charge layers using gas and liquid phase coatings Mar 21, 2022 Issued
Array ( [id] => 18615834 [patent_doc_number] => 20230282573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => INTERCONNECT FEATURE WITH NARROW TOP SECTION AND WIDE BOTTOM SECTION [patent_app_type] => utility [patent_app_number] => 17/685536 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13020 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685536 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685536
INTERCONNECT FEATURE WITH NARROW TOP SECTION AND WIDE BOTTOM SECTION Mar 2, 2022 Pending
Array ( [id] => 19436234 [patent_doc_number] => 20240304732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => LOCALIZED AND LOW TEMPERATURE PLANARIZATION OF DIELECTRIC [patent_app_type] => utility [patent_app_number] => 18/269273 [patent_app_country] => US [patent_app_date] => 2021-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18269273 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/269273
LOCALIZED AND LOW TEMPERATURE PLANARIZATION OF DIELECTRIC Dec 22, 2021 Pending
Array ( [id] => 18456434 [patent_doc_number] => 20230197716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => TRANSISTORS WITH EPITAXIAL SOURCE/DRAIN LINER FOR IMPROVED CONTACT RESISTANCE [patent_app_type] => utility [patent_app_number] => 17/559719 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559719 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559719
TRANSISTORS WITH EPITAXIAL SOURCE/DRAIN LINER FOR IMPROVED CONTACT RESISTANCE Dec 21, 2021 Pending
Array ( [id] => 17692562 [patent_doc_number] => 20220199855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => NITRIDE SEMICONDUCTOR LIGHT EMITTING ELEMENT [patent_app_type] => utility [patent_app_number] => 17/557221 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557221 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557221
Nitride semiconductor light emitting element Dec 20, 2021 Issued
Array ( [id] => 18456572 [patent_doc_number] => 20230197854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => INTEGRATED CIRCUIT STRUCTURES HAVING DIELECTRIC ANCHOR AND CONFINED EPITAXIAL SOURCE OR DRAIN STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/553161 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16731 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/553161
INTEGRATED CIRCUIT STRUCTURES HAVING DIELECTRIC ANCHOR AND CONFINED EPITAXIAL SOURCE OR DRAIN STRUCTURE Dec 15, 2021 Pending
Array ( [id] => 17477393 [patent_doc_number] => 20220084897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/538014 [patent_app_country] => US [patent_app_date] => 2021-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17538014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/538014
Semiconductor structure Nov 29, 2021 Issued
Array ( [id] => 19108810 [patent_doc_number] => 11961925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Engineered nanostructured passivated contacts and method of making the same [patent_app_type] => utility [patent_app_number] => 17/516533 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13433 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/516533
Engineered nanostructured passivated contacts and method of making the same Oct 31, 2021 Issued
Array ( [id] => 19030026 [patent_doc_number] => 11929395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-12 [patent_title] => Superjunction transistor device [patent_app_type] => utility [patent_app_number] => 17/513344 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 12213 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17513344 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/513344
Superjunction transistor device Oct 27, 2021 Issued
Array ( [id] => 18570806 [patent_doc_number] => 20230261143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/026448 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 24204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18026448 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/026448
Display device Sep 6, 2021 Issued
Array ( [id] => 20566056 [patent_doc_number] => 12568680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Nickel silicide in bipolar complementary-metal-oxide-semiconductor (BiCMOS) device [patent_app_type] => utility [patent_app_number] => 17/464046 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464046
Nickel silicide in bipolar complementary-metal-oxide-semiconductor (BiCMOS) device Aug 31, 2021 Issued
Array ( [id] => 17263082 [patent_doc_number] => 20210376067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-02 [patent_title] => FABRICATION OF LATERAL SUPERJUNCTION DEVICES USING SELECTIVE EPITAXY [patent_app_type] => utility [patent_app_number] => 17/400928 [patent_app_country] => US [patent_app_date] => 2021-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17400928 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/400928
FABRICATION OF LATERAL SUPERJUNCTION DEVICES USING SELECTIVE EPITAXY Aug 11, 2021 Abandoned
Array ( [id] => 20443232 [patent_doc_number] => 12514079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Display substrate and display device [patent_app_type] => utility [patent_app_number] => 18/016685 [patent_app_country] => US [patent_app_date] => 2021-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 6849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18016685 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/016685
Display substrate and display device Aug 4, 2021 Issued
Array ( [id] => 17217792 [patent_doc_number] => 20210351130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => REDISTRIBUTION LAYER STRUCTURES FOR INTEGRATED CIRCUIT PACKAGE [patent_app_type] => utility [patent_app_number] => 17/366575 [patent_app_country] => US [patent_app_date] => 2021-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17366575 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/366575
Redistribution layer structures for integrated circuit package Jul 1, 2021 Issued
Array ( [id] => 18721454 [patent_doc_number] => 11798808 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-24 [patent_title] => Method of chemical doping that uses CMOS-compatible processes [patent_app_type] => utility [patent_app_number] => 17/360284 [patent_app_country] => US [patent_app_date] => 2021-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 5914 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360284 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/360284
Method of chemical doping that uses CMOS-compatible processes Jun 27, 2021 Issued
Array ( [id] => 19063264 [patent_doc_number] => 11942518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Reduced interfacial area III-nitride material semiconductor structures [patent_app_type] => utility [patent_app_number] => 17/335521 [patent_app_country] => US [patent_app_date] => 2021-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 26919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17335521 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/335521
Reduced interfacial area III-nitride material semiconductor structures May 31, 2021 Issued
Array ( [id] => 19356985 [patent_doc_number] => 12057442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Semiconductor device in a level shifter with electrostatic discharge (ESD) protection circuit and semiconductor chip [patent_app_type] => utility [patent_app_number] => 17/318190 [patent_app_country] => US [patent_app_date] => 2021-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17318190 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/318190
Semiconductor device in a level shifter with electrostatic discharge (ESD) protection circuit and semiconductor chip May 11, 2021 Issued
Array ( [id] => 16951916 [patent_doc_number] => 20210210608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => Source/Drain Feature to Contact Interfaces [patent_app_type] => utility [patent_app_number] => 17/189093 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8455 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189093 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189093
Source/drain feature to contact interfaces Feb 28, 2021 Issued
Array ( [id] => 18639446 [patent_doc_number] => 11764066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-19 [patent_title] => Peeling method for peeling off substrate from support plate [patent_app_type] => utility [patent_app_number] => 17/180295 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7013 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180295 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180295
Peeling method for peeling off substrate from support plate Feb 18, 2021 Issued
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