Search

Paul J. Killos

Examiner (ID: 19505)

Most Active Art Unit
1206
Art Unit(s)
1206, 1204, 1625, 1623, 1621
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20515197 [patent_doc_number] => 20260039300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => VOLTAGE LEVEL SHIFTERS AND OUTPUT DRIVER INCLUDING VOLTAGE LEVEL SHIFTERS FOR LOW POWER RESET AND HOLD [patent_app_type] => utility [patent_app_number] => 18/792689 [patent_app_country] => US [patent_app_date] => 2024-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18792689 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/792689
Voltage level shifters and output driver including voltage level shifters for low power reset and hold Aug 1, 2024 Issued
Array ( [id] => 19647301 [patent_doc_number] => 20240421821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => GPIO DRIVER WITH LOW LATENCY [patent_app_type] => utility [patent_app_number] => 18/739245 [patent_app_country] => US [patent_app_date] => 2024-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2580 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18739245 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/739245
GPIO DRIVER WITH LOW LATENCY Jun 9, 2024 Pending
Array ( [id] => 19468207 [patent_doc_number] => 20240321877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => Reference Voltage Circuit [patent_app_type] => utility [patent_app_number] => 18/614055 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4666 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614055 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/614055
Reference Voltage Circuit Mar 21, 2024 Pending
Array ( [id] => 19336255 [patent_doc_number] => 20240250685 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => LEVEL SHIFTER WITH AUTOMATIC DIRECTION SENSING [patent_app_type] => utility [patent_app_number] => 18/611223 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5659 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18611223 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/611223
LEVEL SHIFTER WITH AUTOMATIC DIRECTION SENSING Mar 19, 2024 Issued
Array ( [id] => 19365007 [patent_doc_number] => 20240267041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => PASS GATE CIRCUIT ARRANGED FOR PROVIDING AN INPUT TO AN OUTPUT BASED ON A CONTROL SIGNAL, AS WELL AS A CORRESPONDING METHOD AND COMPUTER PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 18/430830 [patent_app_country] => US [patent_app_date] => 2024-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430830 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/430830
PASS GATE CIRCUIT ARRANGED FOR PROVIDING AN INPUT TO AN OUTPUT BASED ON A CONTROL SIGNAL, AS WELL AS A CORRESPONDING METHOD AND COMPUTER PROGRAM PRODUCT Feb 1, 2024 Pending
Array ( [id] => 19725592 [patent_doc_number] => 20250028343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => IN SITU STRAIN COMPENSATION AFE [patent_app_type] => utility [patent_app_number] => 18/394458 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18394458 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/394458
In situ strain compensation AFE Dec 21, 2023 Issued
Array ( [id] => 19238111 [patent_doc_number] => 20240195306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => DEEPLY INTEGRATED VOLTAGE REGULATOR ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/471973 [patent_app_country] => US [patent_app_date] => 2023-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18471973 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/471973
Deeply integrated voltage regulator architectures Sep 20, 2023 Issued
Array ( [id] => 19306981 [patent_doc_number] => 20240235561 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => SAMPLING FRACTIONAL-N PHASE-LOCKED LOOP WITH FEEDBACK SPUR COMPENSATION [patent_app_type] => utility [patent_app_number] => 17/970477 [patent_app_country] => US [patent_app_date] => 2022-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17970477 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/970477
SAMPLING FRACTIONAL-N PHASE-LOCKED LOOP WITH FEEDBACK SPUR COMPENSATION Oct 19, 2022 Pending
Array ( [id] => 19306981 [patent_doc_number] => 20240235561 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => SAMPLING FRACTIONAL-N PHASE-LOCKED LOOP WITH FEEDBACK SPUR COMPENSATION [patent_app_type] => utility [patent_app_number] => 17/970477 [patent_app_country] => US [patent_app_date] => 2022-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17970477 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/970477
SAMPLING FRACTIONAL-N PHASE-LOCKED LOOP WITH FEEDBACK SPUR COMPENSATION Oct 18, 2022 Pending
Array ( [id] => 19500996 [patent_doc_number] => 20240340014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => CIRCUIT ARRANGEMENT, TIME-MODE ARITHMETIC UNIT, ALL-DIGITAL PHASE-LOCKED LOOP, AND CORRESPONDING METHODS [patent_app_type] => utility [patent_app_number] => 18/293368 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16142 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18293368 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/293368
CIRCUIT ARRANGEMENT, TIME-MODE ARITHMETIC UNIT, ALL-DIGITAL PHASE-LOCKED LOOP, AND CORRESPONDING METHODS Aug 4, 2022 Pending
Array ( [id] => 18624293 [patent_doc_number] => 11757355 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-12 [patent_title] => Clock data recovery circuit including charge pump having reduced glitch current [patent_app_type] => utility [patent_app_number] => 17/539878 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3628 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539878 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/539878
Clock data recovery circuit including charge pump having reduced glitch current Nov 30, 2021 Issued
Array ( [id] => 17390245 [patent_doc_number] => 20220038097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => SWITCH FET BODY CURRENT MANAGEMENT DEVICES AND METHODS [patent_app_type] => utility [patent_app_number] => 17/386374 [patent_app_country] => US [patent_app_date] => 2021-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17386374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/386374
SWITCH FET BODY CURRENT MANAGEMENT DEVICES AND METHODS Jul 26, 2021 Abandoned
Array ( [id] => 16889552 [patent_doc_number] => 20210175749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => Wireless Power Systems [patent_app_type] => utility [patent_app_number] => 17/183167 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17183167 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/183167
Wireless Power Systems Feb 22, 2021 Abandoned
Array ( [id] => 17233129 [patent_doc_number] => 20210359686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => CLOCKED LATCH CIRCUIT AND A CLOCK GENERATING CIRCUIT USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/034796 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13834 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034796 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034796
CLOCKED LATCH CIRCUIT AND A CLOCK GENERATING CIRCUIT USING THE SAME Sep 27, 2020 Abandoned
Array ( [id] => 16078501 [patent_doc_number] => 20200193237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => ENSEMBLE MODEL FOR IMAGE RECOGNITION PROCESSING [patent_app_type] => utility [patent_app_number] => 16/799528 [patent_app_country] => US [patent_app_date] => 2020-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16799528 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/799528
Ensemble model for image recognition processing Feb 23, 2020 Issued
Array ( [id] => 15998859 [patent_doc_number] => 20200175300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => METHOD AND SYSTEM FOR OPTICAL CHARACTER RECOGNITION OF SERIES OF IMAGES [patent_app_type] => utility [patent_app_number] => 16/780899 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780899 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/780899
Method and system for optical character recognition of series of images Feb 2, 2020 Issued
Array ( [id] => 15805679 [patent_doc_number] => 20200125982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => SYSTEM AND METHOD FOR UNSUPERVISED DOMAIN ADAPTATION VIA SLICED-WASSERSTEIN DISTANCE [patent_app_type] => utility [patent_app_number] => 16/719668 [patent_app_country] => US [patent_app_date] => 2019-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16719668 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/719668
System and method for unsupervised domain adaptation via sliced-wasserstein distance Dec 17, 2019 Issued
Array ( [id] => 16637541 [patent_doc_number] => 10916053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-09 [patent_title] => Systems and methods for constructing a three-dimensional model from two-dimensional images [patent_app_type] => utility [patent_app_number] => 16/696468 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11059 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16696468 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/696468
Systems and methods for constructing a three-dimensional model from two-dimensional images Nov 25, 2019 Issued
Array ( [id] => 15563127 [patent_doc_number] => 20200065975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => HUMAN ACTION RECOGNITION IN DRONE VIDEOS [patent_app_type] => utility [patent_app_number] => 16/515713 [patent_app_country] => US [patent_app_date] => 2019-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16515713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/515713
Human action recognition in drone videos Jul 17, 2019 Issued
Array ( [id] => 14968033 [patent_doc_number] => 20190311495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => METHOD AND APPARATUS FOR AUTOMATIC INTRINSIC CAMERA CALIBRATION USING IMAGES OF A PLANAR CALIBRATION PATTERN [patent_app_type] => utility [patent_app_number] => 16/448871 [patent_app_country] => US [patent_app_date] => 2019-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8118 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16448871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/448871
Method and apparatus for automatic intrinsic camera calibration using images of a planar calibration pattern Jun 20, 2019 Issued
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