Search

Paul J Killos

Examiner (ID: 6560)

Most Active Art Unit
1206
Art Unit(s)
1623, 1621, 1625, 1206, 1204
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16080625 [patent_doc_number] => 20200194299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => WAFER DE-CHUCKING DETECTION AND ARCING PREVENTION [patent_app_type] => utility [patent_app_number] => 16/217768 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16217768 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/217768
Wafer de-chucking detection and arcing prevention Dec 11, 2018 Issued
Array ( [id] => 16905014 [patent_doc_number] => 20210183930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => SOLID-STATE IMAGING DEVICE, DISTANCE MEASUREMENT DEVICE, AND MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 16/470099 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16470099 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/470099
SOLID-STATE IMAGING DEVICE, DISTANCE MEASUREMENT DEVICE, AND MANUFACTURING METHOD Dec 11, 2018 Abandoned
Array ( [id] => 17203432 [patent_doc_number] => 20210343527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => PATTERNING FOR SELECTIVE EJECTIONS OF PRINTABLE AMMONIUM-BASED CHALCOGENOMETALATE FLUIDS [patent_app_type] => utility [patent_app_number] => 17/286574 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17286574 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/286574
PATTERNING FOR SELECTIVE EJECTIONS OF PRINTABLE AMMONIUM-BASED CHALCOGENOMETALATE FLUIDS Dec 9, 2018 Pending
Array ( [id] => 14573721 [patent_doc_number] => 20190214468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => Gallium nitride materials and methods [patent_app_type] => utility [patent_app_number] => 16/209858 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16209858 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/209858
Gallium nitride materials and methods Dec 3, 2018 Abandoned
Array ( [id] => 16000831 [patent_doc_number] => 20200176286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => MODULE STRUCTURES WITH COMPONENT ON SUBSTRATE POST [patent_app_type] => utility [patent_app_number] => 16/207738 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16207738 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/207738
MODULE STRUCTURES WITH COMPONENT ON SUBSTRATE POST Dec 2, 2018 Abandoned
Array ( [id] => 14382701 [patent_doc_number] => 20190165263 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => METHODS OF FORMING A MEMORY STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/202891 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202891 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202891
Methods of forming a memory structure Nov 27, 2018 Issued
Array ( [id] => 15939093 [patent_doc_number] => 20200161180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-21 [patent_title] => TALL TRENCHES FOR VIA CHAMFERLESS AND SELF FORMING BARRIER [patent_app_type] => utility [patent_app_number] => 16/197558 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197558 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197558
Tall trenches for via chamferless and self forming barrier Nov 20, 2018 Issued
Array ( [id] => 16448266 [patent_doc_number] => 10840197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Package structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/197334 [patent_app_country] => US [patent_app_date] => 2018-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 12561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197334 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197334
Package structure and manufacturing method thereof Nov 19, 2018 Issued
Array ( [id] => 14079739 [patent_doc_number] => 20190088757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => ONE-DIMENSIONAL NANOSTRUCTURE GROWTH ON GRAPHENE AND DEVICES THEREOF [patent_app_type] => utility [patent_app_number] => 16/195591 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16195591 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/195591
One-dimensional nanostructure growth on graphene and devices thereof Nov 18, 2018 Issued
Array ( [id] => 14110639 [patent_doc_number] => 20190096995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/186764 [patent_app_country] => US [patent_app_date] => 2018-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16186764 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/186764
Semiconductor structure and manufacturing method thereof Nov 11, 2018 Issued
Array ( [id] => 16293714 [patent_doc_number] => 10770570 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => FinFET device and methods of forming [patent_app_type] => utility [patent_app_number] => 16/173642 [patent_app_country] => US [patent_app_date] => 2018-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 68 [patent_no_of_words] => 12372 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16173642 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/173642
FinFET device and methods of forming Oct 28, 2018 Issued
Array ( [id] => 17254224 [patent_doc_number] => 11189724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Method of forming a top epitaxy source/drain structure for a vertical transistor [patent_app_type] => utility [patent_app_number] => 16/169589 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5280 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169589 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169589
Method of forming a top epitaxy source/drain structure for a vertical transistor Oct 23, 2018 Issued
Array ( [id] => 14238049 [patent_doc_number] => 20190131197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => QUAD FLAT NO-LEAD PACKAGE [patent_app_type] => utility [patent_app_number] => 16/169700 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169700
QUAD FLAT NO-LEAD PACKAGE Oct 23, 2018 Abandoned
Array ( [id] => 14079803 [patent_doc_number] => 20190088789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => SEMICONDUCTOR DEVICE HAVING CHANNEL REGIONS [patent_app_type] => utility [patent_app_number] => 16/161765 [patent_app_country] => US [patent_app_date] => 2018-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16161765 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/161765
Semiconductor device having channel regions Oct 15, 2018 Issued
Array ( [id] => 13936499 [patent_doc_number] => 20190051765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-14 [patent_title] => MONOLITHIC INTEGRATION TECHNIQUES FOR FABRICATING PHOTODETECTORS WITH TRANSISTORS ON SAME SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/157032 [patent_app_country] => US [patent_app_date] => 2018-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157032 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/157032
MONOLITHIC INTEGRATION TECHNIQUES FOR FABRICATING PHOTODETECTORS WITH TRANSISTORS ON SAME SUBSTRATE Oct 9, 2018 Abandoned
Array ( [id] => 16048299 [patent_doc_number] => 10686035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Nano-tube MOSFET technology and devices [patent_app_type] => utility [patent_app_number] => 16/155066 [patent_app_country] => US [patent_app_date] => 2018-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 57 [patent_no_of_words] => 9407 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16155066 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/155066
Nano-tube MOSFET technology and devices Oct 8, 2018 Issued
Array ( [id] => 15807995 [patent_doc_number] => 20200127140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => ARRAY SUBSTRATE, MANUFACTURING METHOD FOR SAME, AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 16/325394 [patent_app_country] => US [patent_app_date] => 2018-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16325394 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/325394
ARRAY SUBSTRATE, MANUFACTURING METHOD FOR SAME, AND DISPLAY PANEL Oct 8, 2018 Abandoned
Array ( [id] => 15889667 [patent_doc_number] => 10651189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Method for producing pillar-shaped semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/148099 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 100 [patent_no_of_words] => 17827 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148099 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/148099
Method for producing pillar-shaped semiconductor memory device Sep 30, 2018 Issued
Array ( [id] => 16819893 [patent_doc_number] => 11004731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/135686 [patent_app_country] => US [patent_app_date] => 2018-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 41 [patent_no_of_words] => 12300 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16135686 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/135686
Semiconductor device Sep 18, 2018 Issued
Array ( [id] => 13781325 [patent_doc_number] => 20190004201 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => POWER MOSFET WITH A DEEP SOURCE CONTACT [patent_app_type] => utility [patent_app_number] => 16/101867 [patent_app_country] => US [patent_app_date] => 2018-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16101867 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/101867
Power MOSFET with a deep source contact Aug 12, 2018 Issued
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