Search

Paul J Killos

Examiner (ID: 6560)

Most Active Art Unit
1206
Art Unit(s)
1623, 1621, 1625, 1206, 1204
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15688303 [patent_doc_number] => 20200098815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 16/495335 [patent_app_country] => US [patent_app_date] => 2018-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 48760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16495335 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/495335
Solid-state imaging device and electronic apparatus Mar 22, 2018 Issued
Array ( [id] => 16202145 [patent_doc_number] => 10727325 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-28 [patent_title] => Nanostructure-based vacuum channel transistor [patent_app_type] => utility [patent_app_number] => 15/933240 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5008 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15933240 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/933240
Nanostructure-based vacuum channel transistor Mar 21, 2018 Issued
Array ( [id] => 17716622 [patent_doc_number] => 11380621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Susceptor for holding a semiconductor wafer having an orientation notch, a method for depositing a layer on a semiconductor wafer, and semiconductor wafer [patent_app_type] => utility [patent_app_number] => 15/928534 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3582 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15928534 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/928534
Susceptor for holding a semiconductor wafer having an orientation notch, a method for depositing a layer on a semiconductor wafer, and semiconductor wafer Mar 21, 2018 Issued
Array ( [id] => 15315887 [patent_doc_number] => 10522661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Integrated strained stacked nanosheet FET [patent_app_type] => utility [patent_app_number] => 15/926151 [patent_app_country] => US [patent_app_date] => 2018-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4529 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15926151 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/926151
Integrated strained stacked nanosheet FET Mar 19, 2018 Issued
Array ( [id] => 15618477 [patent_doc_number] => 20200079643 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-12 [patent_title] => SYSTEMS AND METHODS FOR FABRICATING 3D SOFT MICROSTRUCTURES [patent_app_type] => utility [patent_app_number] => 16/493746 [patent_app_country] => US [patent_app_date] => 2018-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8957 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16493746 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/493746
Systems and methods for fabricating 3D soft microstructures Mar 13, 2018 Issued
Array ( [id] => 13435367 [patent_doc_number] => 20180269226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 15/918072 [patent_app_country] => US [patent_app_date] => 2018-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15918072 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/918072
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME Mar 11, 2018 Abandoned
Array ( [id] => 15547737 [patent_doc_number] => 10573659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Semiconductor memory device of three-dimensional structure [patent_app_type] => utility [patent_app_number] => 15/915136 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9101 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15915136 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/915136
Semiconductor memory device of three-dimensional structure Mar 7, 2018 Issued
Array ( [id] => 16846175 [patent_doc_number] => 11018272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-25 [patent_title] => Methods for forming metal electrodes concurrently on silicon regions of opposite polarity [patent_app_type] => utility [patent_app_number] => 16/496284 [patent_app_country] => US [patent_app_date] => 2018-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 13815 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16496284 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/496284
Methods for forming metal electrodes concurrently on silicon regions of opposite polarity Mar 7, 2018 Issued
Array ( [id] => 13878913 [patent_doc_number] => 20190035797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/914130 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13615 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914130 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914130
Semiconductor device and method of manufacturing the same Mar 6, 2018 Issued
Array ( [id] => 14843199 [patent_doc_number] => 20190280000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => MULTI-TIER MEMORY DEVICE WITH ROUNDED TOP PART OF JOINT STRUCTURE AND METHODS OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 15/914560 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20176 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15914560 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/914560
Multi-tier memory device with rounded top part of joint structure and methods of making the same Mar 6, 2018 Issued
Array ( [id] => 14955373 [patent_doc_number] => 10438966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-08 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/913947 [patent_app_country] => US [patent_app_date] => 2018-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 25 [patent_no_of_words] => 8462 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15913947 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/913947
Semiconductor device Mar 6, 2018 Issued
Array ( [id] => 14859467 [patent_doc_number] => 10418470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Semiconductor device having IGBT portion and diode portion [patent_app_type] => utility [patent_app_number] => 15/912600 [patent_app_country] => US [patent_app_date] => 2018-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6630 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 501 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15912600 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/912600
Semiconductor device having IGBT portion and diode portion Mar 5, 2018 Issued
Array ( [id] => 14812839 [patent_doc_number] => 20190273029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-05 [patent_title] => ELECTRONIC DEVICE WITH A PACKAGE-LEVEL THERMAL REGULATOR MECHANISM AND ASSOCIATED SYSTEMS, DEVICES, AND METHODS [patent_app_type] => utility [patent_app_number] => 15/910590 [patent_app_country] => US [patent_app_date] => 2018-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15910590 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/910590
Electronic device with a package-level thermal regulator mechanism and associated systems, devices, and methods Mar 1, 2018 Issued
Array ( [id] => 13996305 [patent_doc_number] => 20190067310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/908006 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6623 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15908006 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/908006
Method for manufacturing semiconductor device and semiconductor device Feb 27, 2018 Issued
Array ( [id] => 14785127 [patent_doc_number] => 20190267461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE WITH SELF-ALIGNED DRAIN SELECT LEVEL ISOLATION STRUCTURES AND METHOD OF MAKING THEREOF [patent_app_type] => utility [patent_app_number] => 15/906109 [patent_app_country] => US [patent_app_date] => 2018-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19582 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15906109 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/906109
Three-dimensional memory device with self-aligned drain select level isolation structures and method of making thereof Feb 26, 2018 Issued
Array ( [id] => 14079571 [patent_doc_number] => 20190088673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 15/904637 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904637 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/904637
Semiconductor memory device Feb 25, 2018 Issued
Array ( [id] => 13878917 [patent_doc_number] => 20190035799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => SEAL METHOD TO INTEGRATE NON-VOLATILE MEMORY (NVM) INTO LOGIC OR BIPOLAR CMOS DMOS (BCD) TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 15/904836 [patent_app_country] => US [patent_app_date] => 2018-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15904836 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/904836
Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology Feb 25, 2018 Issued
Array ( [id] => 14333165 [patent_doc_number] => 10297611 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-21 [patent_title] => Transistors and arrays of elevationally-extending strings of memory cells [patent_app_type] => utility [patent_app_number] => 15/903307 [patent_app_country] => US [patent_app_date] => 2018-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5927 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15903307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/903307
Transistors and arrays of elevationally-extending strings of memory cells Feb 22, 2018 Issued
Array ( [id] => 13862119 [patent_doc_number] => 10192784 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-29 [patent_title] => Three-dimensional memory device containing self-aligned contact via structures and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/902169 [patent_app_country] => US [patent_app_date] => 2018-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 76 [patent_figures_cnt] => 85 [patent_no_of_words] => 20278 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15902169 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/902169
Three-dimensional memory device containing self-aligned contact via structures and methods of manufacturing the same Feb 21, 2018 Issued
Array ( [id] => 13485433 [patent_doc_number] => 20180294259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/901911 [patent_app_country] => US [patent_app_date] => 2018-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9227 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15901911 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/901911
Semiconductor device having a sense diode portion Feb 21, 2018 Issued
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