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Paul J Killos

Examiner (ID: 6560)

Most Active Art Unit
1206
Art Unit(s)
1623, 1621, 1625, 1206, 1204
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15296723 [patent_doc_number] => 20190391497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => METHOD OF FORMING RESIST PATTERN [patent_app_type] => utility [patent_app_number] => 16/490665 [patent_app_country] => US [patent_app_date] => 2018-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16490665 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/490665
METHOD OF FORMING RESIST PATTERN Feb 20, 2018 Abandoned
Array ( [id] => 13393099 [patent_doc_number] => 20180248092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => LIGHT SENSOR LEAD FRAME SUBSTRATE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/900685 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2688 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900685 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900685
LIGHT SENSOR LEAD FRAME SUBSTRATE AND MANUFACTURING METHOD THEREOF Feb 19, 2018 Abandoned
Array ( [id] => 18705266 [patent_doc_number] => 11791788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Parametric amplifier [patent_app_type] => utility [patent_app_number] => 16/487071 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4300 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16487071 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/487071
Parametric amplifier Feb 19, 2018 Issued
Array ( [id] => 13420103 [patent_doc_number] => 20180261594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/889626 [patent_app_country] => US [patent_app_date] => 2018-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5587 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15889626 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/889626
SEMICONDUCTOR DEVICE Feb 5, 2018 Abandoned
Array ( [id] => 13349443 [patent_doc_number] => 20180226261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => METHOD OF ANISOTROPICALLY ETCHING GRAPHENE [patent_app_type] => utility [patent_app_number] => 15/888468 [patent_app_country] => US [patent_app_date] => 2018-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15888468 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/888468
METHOD OF ANISOTROPICALLY ETCHING GRAPHENE Feb 4, 2018 Abandoned
Array ( [id] => 13435319 [patent_doc_number] => 20180269202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/883537 [patent_app_country] => US [patent_app_date] => 2018-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15883537 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/883537
Semiconductor device Jan 29, 2018 Issued
Array ( [id] => 15475265 [patent_doc_number] => 10553517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => High power module semiconductor package with multiple submodules [patent_app_type] => utility [patent_app_number] => 15/874355 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 56 [patent_no_of_words] => 10910 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874355 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/874355
High power module semiconductor package with multiple submodules Jan 17, 2018 Issued
Array ( [id] => 16233932 [patent_doc_number] => 10741495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Structure and method to reduce shorts and contact resistance in semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/873946 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873946 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/873946
Structure and method to reduce shorts and contact resistance in semiconductor devices Jan 17, 2018 Issued
Array ( [id] => 12800785 [patent_doc_number] => 20180158764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => 3D CHIP ASSEMBLIES USING STACKED LEADFRAMES [patent_app_type] => utility [patent_app_number] => 15/874783 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15874783 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/874783
3D CHIP ASSEMBLIES USING STACKED LEADFRAMES Jan 17, 2018 Abandoned
Array ( [id] => 14276651 [patent_doc_number] => 20190135610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/873937 [patent_app_country] => US [patent_app_date] => 2018-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15873937 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/873937
Structure and formation method of semiconductor device structure Jan 17, 2018 Issued
Array ( [id] => 15170531 [patent_doc_number] => 10490773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Organic light-emitting display device [patent_app_type] => utility [patent_app_number] => 15/871109 [patent_app_country] => US [patent_app_date] => 2018-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7559 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15871109 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/871109
Organic light-emitting display device Jan 14, 2018 Issued
Array ( [id] => 12739027 [patent_doc_number] => 20180138176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/870649 [patent_app_country] => US [patent_app_date] => 2018-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15870649 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/870649
Semiconductor device and a method for fabricating the same Jan 11, 2018 Issued
Array ( [id] => 14644637 [patent_doc_number] => 10367069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Fabrication of vertical field effect transistor structure with controlled gate length [patent_app_type] => utility [patent_app_number] => 15/852956 [patent_app_country] => US [patent_app_date] => 2017-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 8713 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15852956 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/852956
Fabrication of vertical field effect transistor structure with controlled gate length Dec 21, 2017 Issued
Array ( [id] => 12739441 [patent_doc_number] => 20180138314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => POWER MOSFETS MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 15/848776 [patent_app_country] => US [patent_app_date] => 2017-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15848776 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/848776
Power MOSFETs manufacturing method Dec 19, 2017 Issued
Array ( [id] => 17847138 [patent_doc_number] => 11436516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-06 [patent_title] => Integrating circuit elements in a stacked quantum computing device [patent_app_type] => utility [patent_app_number] => 16/493400 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 8698 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16493400 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/493400
Integrating circuit elements in a stacked quantum computing device Dec 14, 2017 Issued
Array ( [id] => 12631452 [patent_doc_number] => 20180102314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-12 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/837828 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837828 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837828
SEMICONDUCTOR DEVICE Dec 10, 2017 Abandoned
Array ( [id] => 12823723 [patent_doc_number] => 20180166413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => ELECTRICALLY CONDUCTIVE BOND BETWEEN AT LEAST TWO ELECTRICAL COMPONENTS AT A CARRIER MOUNTED WITH ELECTRONIC AND/OR ELECTRICAL DEVICES, SAID BOND BEING FORMED BY A BOND WIRE [patent_app_type] => utility [patent_app_number] => 15/837280 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837280 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837280
ELECTRICALLY CONDUCTIVE BOND BETWEEN AT LEAST TWO ELECTRICAL COMPONENTS AT A CARRIER MOUNTED WITH ELECTRONIC AND/OR ELECTRICAL DEVICES, SAID BOND BEING FORMED BY A BOND WIRE Dec 10, 2017 Abandoned
Array ( [id] => 15688689 [patent_doc_number] => 20200099008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => ENCAPSULATING COMPOSITION [patent_app_type] => utility [patent_app_number] => 16/467375 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16467375 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/467375
Encapsulating composition Dec 10, 2017 Issued
Array ( [id] => 15641519 [patent_doc_number] => 10593771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-17 [patent_title] => Vertical fin-type bipolar junction transistor with self-aligned base contact [patent_app_type] => utility [patent_app_number] => 15/837321 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837321 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837321
Vertical fin-type bipolar junction transistor with self-aligned base contact Dec 10, 2017 Issued
Array ( [id] => 14268105 [patent_doc_number] => 10283625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Integrated strained stacked nanosheet FET [patent_app_type] => utility [patent_app_number] => 15/835526 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4441 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15835526 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/835526
Integrated strained stacked nanosheet FET Dec 7, 2017 Issued
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