Paul J Killos

Array ( [id] => 16567057 [patent_doc_number] => 10892434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Light-emitting electrochemical cell [patent_app_type] => utility [patent_app_number] => 16/477879 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 38 [patent_no_of_words] => 9985 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16477879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12716806 [patent_doc_number] => 20180130768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => Substrate Based Fan-Out Wafer Level Packaging [patent_app_type] => utility [patent_app_number] => 15/399525 [patent_app_country] => US [patent_app_date] => 2017-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2324 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15399525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12032142 [patent_doc_number] => 20170322242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'APPARATUS FOR PREDICTING POWER LOSS OF TRANSFORMER' [patent_app_type] => utility [patent_app_number] => 15/394920 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3960 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15394920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16888901 [patent_doc_number] => 20210175098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 16/071104 [patent_app_country] => US [patent_app_date] => 2016-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13301 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16071104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12849496 [patent_doc_number] => 20180175005 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => THERMAL DISSIPATION USING ANISOTROPIC CONDUCTIVE MATERIAL [patent_app_type] => utility [patent_app_number] => 15/386802 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15386802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15250139 [patent_doc_number] => 10510598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Self-aligned spacers and method forming same [patent_app_type] => utility [patent_app_number] => 15/386952 [patent_app_country] => US [patent_app_date] => 2016-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 4708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15386952 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12823552 [patent_doc_number] => 20180166356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => FAN-OUT CIRCUIT PACKAGING WITH INTEGRATED LID [patent_app_type] => utility [patent_app_number] => 15/377496 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15377496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11517654 [patent_doc_number] => 20170084728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'BIDIRECTIONAL MOS DEVICE AND METHOD FOR PREPARING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/372352 [patent_app_country] => US [patent_app_date] => 2016-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8739 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15372352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13709225 [patent_doc_number] => 20170365567 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => FAN-OUT SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 15/369518 [patent_app_country] => US [patent_app_date] => 2016-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15369518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16501225 [patent_doc_number] => 10866608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Apparatus and method of voltage regulation control for integrated circuit [patent_app_type] => utility [patent_app_number] => 15/365675 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3409 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12774679 [patent_doc_number] => 20180150061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => SYSTEM AND METHOD FOR USING BLUETOOTH COMMUNICATION IN INDUSTRIAL PROCESS CONTROL AND AUTOMATION SYSTEMS [patent_app_type] => utility [patent_app_number] => 15/362078 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15362078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12033853 [patent_doc_number] => 20170323952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'Integrated strained stacked nanosheet FET' [patent_app_type] => utility [patent_app_number] => 15/356979 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11650686 [patent_doc_number] => 20170146587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'METHOD AND DEVICE FOR DETERMINING THE FAULT LOCATION IN THE CASE OF A FAULT ON AN ELECTRIC LINE' [patent_app_type] => utility [patent_app_number] => 15/356792 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6557 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12229913 [patent_doc_number] => 09917162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Fabrication of vertical field effect transistor structure with controlled gate length' [patent_app_type] => utility [patent_app_number] => 15/353352 [patent_app_country] => US [patent_app_date] => 2016-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 8994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15353352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16132587 [patent_doc_number] => 10700061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-30 [patent_title] => Semiconductor device comprising a first transistor and a second transistor [patent_app_type] => utility [patent_app_number] => 15/351816 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9675 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12738742 [patent_doc_number] => 20180138081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => SEMICONDUCTOR STRUCTURES AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/352125 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15352125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11732919 [patent_doc_number] => 20170194362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'DISPLAY SUBSTRATE AND FABRICATION METHOD THEREOF, AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/351878 [patent_app_country] => US [patent_app_date] => 2016-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4456 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14204913 [patent_doc_number] => 10269577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Semiconductor devices and methods for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/351289 [patent_app_country] => US [patent_app_date] => 2016-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 8568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15351289 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12716662 [patent_doc_number] => 20180130720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-10 [patent_title] => Substrate Based Fan-Out Wafer Level Packaging [patent_app_type] => utility [patent_app_number] => 15/347253 [patent_app_country] => US [patent_app_date] => 2016-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15347253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11502924 [patent_doc_number] => 20170077109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/343591 [patent_app_country] => US [patent_app_date] => 2016-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8292 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15343591 [rel_patent_id] =>[rel_patent_doc_number] =>)