Paul J Killos
Examiner (ID: 14937)
Most Active Art Unit | 1206 |
Art Unit(s) | 1623, 1621, 1625, 1204, 1206 |
Total Applications | 2978 |
Issued Applications | 2595 |
Pending Applications | 134 |
Abandoned Applications | 247 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 7220533
[patent_doc_number] => 20050077601
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => 'Organic electronic devices with low thermal resistance and processes for forming and using the same'
[patent_app_type] => utility
[patent_app_number] => 10/683828
[patent_app_country] => US
[patent_app_date] => 2003-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 13637
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20050077601.pdf
[firstpage_image] =>[orig_patent_app_number] => 10683828
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/683828 | Process for making an organic electronic device having a roughened surface heat sink | Oct 9, 2003 | Issued |
Array
(
[id] => 790846
[patent_doc_number] => 06984870
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-10
[patent_title] => 'High speed cross-point switch using SiGe HBT technology'
[patent_app_type] => utility
[patent_app_number] => 10/682949
[patent_app_country] => US
[patent_app_date] => 2003-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3282
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/984/06984870.pdf
[firstpage_image] =>[orig_patent_app_number] => 10682949
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/682949 | High speed cross-point switch using SiGe HBT technology | Oct 8, 2003 | Issued |
Array
(
[id] => 7220375
[patent_doc_number] => 20050077574
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-14
[patent_title] => '1T/0C RAM cell with a wrapped-around gate device structure'
[patent_app_type] => utility
[patent_app_number] => 10/680158
[patent_app_country] => US
[patent_app_date] => 2003-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6460
[patent_no_of_claims] => 110
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0077/20050077574.pdf
[firstpage_image] =>[orig_patent_app_number] => 10680158
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/680158 | 1T/0C RAM cell with a wrapped-around gate device structure | Oct 7, 2003 | Abandoned |
Array
(
[id] => 509826
[patent_doc_number] => 07195992
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-03-27
[patent_title] => 'Method of uniform seeding to control grain and defect density of crystallized silicon for use in sub-micron thin film transistors'
[patent_app_type] => utility
[patent_app_number] => 10/681509
[patent_app_country] => US
[patent_app_date] => 2003-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 6343
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/195/07195992.pdf
[firstpage_image] =>[orig_patent_app_number] => 10681509
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/681509 | Method of uniform seeding to control grain and defect density of crystallized silicon for use in sub-micron thin film transistors | Oct 6, 2003 | Issued |
Array
(
[id] => 7280905
[patent_doc_number] => 20040063282
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-01
[patent_title] => 'Nanometer-scale semiconductor devices and method of making'
[patent_app_type] => new
[patent_app_number] => 10/668558
[patent_app_country] => US
[patent_app_date] => 2003-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 8416
[patent_no_of_claims] => 56
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0063/20040063282.pdf
[firstpage_image] =>[orig_patent_app_number] => 10668558
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/668558 | Nanometer-scale semiconductor devices and method of making | Sep 21, 2003 | Abandoned |
Array
(
[id] => 779542
[patent_doc_number] => 06995410
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-07
[patent_title] => 'NAND flash memory with unequal spacing between signal lines'
[patent_app_type] => utility
[patent_app_number] => 10/664538
[patent_app_country] => US
[patent_app_date] => 2003-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 5924
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/995/06995410.pdf
[firstpage_image] =>[orig_patent_app_number] => 10664538
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/664538 | NAND flash memory with unequal spacing between signal lines | Sep 18, 2003 | Issued |
Array
(
[id] => 673011
[patent_doc_number] => 07091573
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-15
[patent_title] => 'Power transistor'
[patent_app_type] => utility
[patent_app_number] => 10/666228
[patent_app_country] => US
[patent_app_date] => 2003-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3001
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/091/07091573.pdf
[firstpage_image] =>[orig_patent_app_number] => 10666228
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/666228 | Power transistor | Sep 17, 2003 | Issued |
Array
(
[id] => 730053
[patent_doc_number] => 07042042
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-09
[patent_title] => 'Integrated circuit capacitors having a dielectric layer between a U-shaped lower electrode and a support layer'
[patent_app_type] => utility
[patent_app_number] => 10/665093
[patent_app_country] => US
[patent_app_date] => 2003-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 3650
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/042/07042042.pdf
[firstpage_image] =>[orig_patent_app_number] => 10665093
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/665093 | Integrated circuit capacitors having a dielectric layer between a U-shaped lower electrode and a support layer | Sep 16, 2003 | Issued |
Array
(
[id] => 7280878
[patent_doc_number] => 20040063255
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-01
[patent_title] => 'Thin film transistor structure and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/662909
[patent_app_country] => US
[patent_app_date] => 2003-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3091
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0063/20040063255.pdf
[firstpage_image] =>[orig_patent_app_number] => 10662909
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/662909 | Thin film transistor structure | Sep 14, 2003 | Issued |
Array
(
[id] => 7267820
[patent_doc_number] => 20040056338
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-25
[patent_title] => 'Near chip size semiconductor package'
[patent_app_type] => new
[patent_app_number] => 10/662248
[patent_app_country] => US
[patent_app_date] => 2003-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4140
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0056/20040056338.pdf
[firstpage_image] =>[orig_patent_app_number] => 10662248
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/662248 | Near chip size semiconductor package | Sep 14, 2003 | Issued |
Array
(
[id] => 7615005
[patent_doc_number] => 06897521
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-24
[patent_title] => 'Split gate flash memory cell'
[patent_app_type] => utility
[patent_app_number] => 10/605198
[patent_app_country] => US
[patent_app_date] => 2003-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 6152
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/897/06897521.pdf
[firstpage_image] =>[orig_patent_app_number] => 10605198
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/605198 | Split gate flash memory cell | Sep 14, 2003 | Issued |
Array
(
[id] => 7295937
[patent_doc_number] => 20040124492
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-01
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/660559
[patent_app_country] => US
[patent_app_date] => 2003-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 9094
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20040124492.pdf
[firstpage_image] =>[orig_patent_app_number] => 10660559
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/660559 | Semiconductor device including a gate insulating film on a recess and source and drain extension regions | Sep 11, 2003 | Issued |
Array
(
[id] => 484277
[patent_doc_number] => 07220991
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-22
[patent_title] => 'Thin film transistor array panel for liquid crystal display'
[patent_app_type] => utility
[patent_app_number] => 10/660779
[patent_app_country] => US
[patent_app_date] => 2003-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 78
[patent_figures_cnt] => 79
[patent_no_of_words] => 19557
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/220/07220991.pdf
[firstpage_image] =>[orig_patent_app_number] => 10660779
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/660779 | Thin film transistor array panel for liquid crystal display | Sep 11, 2003 | Issued |
Array
(
[id] => 7212663
[patent_doc_number] => 20050054156
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-10
[patent_title] => 'CAPACITOR AND FABRICATION METHOD USING ULTRA-HIGH VACUUM CVD OF SILICON NITRIDE'
[patent_app_type] => utility
[patent_app_number] => 10/605128
[patent_app_country] => US
[patent_app_date] => 2003-09-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2952
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0054/20050054156.pdf
[firstpage_image] =>[orig_patent_app_number] => 10605128
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/605128 | CAPACITOR AND FABRICATION METHOD USING ULTRA-HIGH VACUUM CVD OF SILICON NITRIDE | Sep 9, 2003 | Abandoned |
Array
(
[id] => 698888
[patent_doc_number] => 07067372
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-27
[patent_title] => 'Method for fabricating a memory cell having a trench'
[patent_app_type] => utility
[patent_app_number] => 10/657929
[patent_app_country] => US
[patent_app_date] => 2003-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 41
[patent_no_of_words] => 7128
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/067/07067372.pdf
[firstpage_image] =>[orig_patent_app_number] => 10657929
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/657929 | Method for fabricating a memory cell having a trench | Sep 8, 2003 | Issued |
Array
(
[id] => 7433872
[patent_doc_number] => 20040065934
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-08
[patent_title] => 'Bidirectional shallow trench superjunction device with resurf region'
[patent_app_type] => new
[patent_app_number] => 10/649929
[patent_app_country] => US
[patent_app_date] => 2003-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 3843
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0065/20040065934.pdf
[firstpage_image] =>[orig_patent_app_number] => 10649929
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/649929 | Bidirectional shallow trench superjunction device with resurf region | Aug 25, 2003 | Issued |
Array
(
[id] => 7445606
[patent_doc_number] => 20040051137
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-03-18
[patent_title] => 'Semiconductor integrated circuit device and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/643718
[patent_app_country] => US
[patent_app_date] => 2003-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 8191
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0051/20040051137.pdf
[firstpage_image] =>[orig_patent_app_number] => 10643718
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/643718 | Method of manufacturing semiconductor integrated circuit device | Aug 18, 2003 | Issued |
Array
(
[id] => 979346
[patent_doc_number] => 06930351
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-16
[patent_title] => 'Semiconductor device with dummy gate electrode'
[patent_app_type] => utility
[patent_app_number] => 10/640019
[patent_app_country] => US
[patent_app_date] => 2003-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 36
[patent_no_of_words] => 7709
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 298
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/930/06930351.pdf
[firstpage_image] =>[orig_patent_app_number] => 10640019
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/640019 | Semiconductor device with dummy gate electrode | Aug 13, 2003 | Issued |
Array
(
[id] => 954106
[patent_doc_number] => 06958521
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-10-25
[patent_title] => 'Shallow trench isolation structure'
[patent_app_type] => utility
[patent_app_number] => 10/639419
[patent_app_country] => US
[patent_app_date] => 2003-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 18
[patent_no_of_words] => 2310
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/958/06958521.pdf
[firstpage_image] =>[orig_patent_app_number] => 10639419
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/639419 | Shallow trench isolation structure | Aug 10, 2003 | Issued |
Array
(
[id] => 782748
[patent_doc_number] => 06991996
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-31
[patent_title] => 'Manufacturing method of semiconductor device and semiconductor chip using SOI substrate, facilitating cleaving'
[patent_app_type] => utility
[patent_app_number] => 10/634839
[patent_app_country] => US
[patent_app_date] => 2003-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3010
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/991/06991996.pdf
[firstpage_image] =>[orig_patent_app_number] => 10634839
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/634839 | Manufacturing method of semiconductor device and semiconductor chip using SOI substrate, facilitating cleaving | Aug 5, 2003 | Issued |