Search

Paul J Killos

Examiner (ID: 14937)

Most Active Art Unit
1206
Art Unit(s)
1623, 1621, 1625, 1204, 1206
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
10/261868 Integrated circuit film substrate having embedded conductive patterns and vias Sep 30, 2002 Abandoned
Array ( [id] => 1015052 [patent_doc_number] => 06894397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Plural semiconductor devices in monolithic flip chip' [patent_app_type] => utility [patent_app_number] => 10/260148 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1663 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/894/06894397.pdf [firstpage_image] =>[orig_patent_app_number] => 10260148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/260148
Plural semiconductor devices in monolithic flip chip Sep 26, 2002 Issued
Array ( [id] => 7278850 [patent_doc_number] => 20040061227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Hardmask employing multiple layers of silicon oxynitride' [patent_app_type] => new [patent_app_number] => 10/256368 [patent_app_country] => US [patent_app_date] => 2002-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20040061227.pdf [firstpage_image] =>[orig_patent_app_number] => 10256368 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/256368
Method for forming a hardmask employing multiple independently formed layers of a pecvd material to reduce pinholes Sep 26, 2002 Issued
Array ( [id] => 6790126 [patent_doc_number] => 20030085470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/254669 [patent_app_country] => US [patent_app_date] => 2002-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20030085470.pdf [firstpage_image] =>[orig_patent_app_number] => 10254669 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/254669
Semiconductor device and method of manufacturing the same Sep 25, 2002 Abandoned
Array ( [id] => 6627996 [patent_doc_number] => 20030102557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Method of processing a semiconductor wafer and substrate for semiconductor wafers used in the same' [patent_app_type] => new [patent_app_number] => 10/252359 [patent_app_country] => US [patent_app_date] => 2002-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4687 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20030102557.pdf [firstpage_image] =>[orig_patent_app_number] => 10252359 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/252359
Method of processing a semiconductor wafer Sep 23, 2002 Issued
Array ( [id] => 5863132 [patent_doc_number] => 20060097262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Thin film transistor array panel' [patent_app_type] => utility [patent_app_number] => 10/522848 [patent_app_country] => US [patent_app_date] => 2002-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6155 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20060097262.pdf [firstpage_image] =>[orig_patent_app_number] => 10522848 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/522848
Thin film transistor array panel with common bars of different widths Sep 17, 2002 Issued
Array ( [id] => 7130138 [patent_doc_number] => 20040041167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Gate dielectric antifuse circuit to protect a high-voltage transistor' [patent_app_type] => new [patent_app_number] => 10/230928 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9516 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20040041167.pdf [firstpage_image] =>[orig_patent_app_number] => 10230928 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230928
Gate dielectric antifuse circuit to protect a high-voltage transistor Aug 28, 2002 Issued
Array ( [id] => 6753406 [patent_doc_number] => 20030001182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Memory integrated circuitry' [patent_app_type] => new [patent_app_number] => 10/232794 [patent_app_country] => US [patent_app_date] => 2002-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2255 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20030001182.pdf [firstpage_image] =>[orig_patent_app_number] => 10232794 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232794
Memory integrated circuitry Aug 27, 2002 Abandoned
Array ( [id] => 7379994 [patent_doc_number] => 20040036095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'DRAM cell with enhanced SER immunity' [patent_app_type] => new [patent_app_number] => 10/064869 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20040036095.pdf [firstpage_image] =>[orig_patent_app_number] => 10064869 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064869
DRAM cell with enhanced SER immunity Aug 25, 2002 Issued
Array ( [id] => 6748043 [patent_doc_number] => 20030042563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Display device, device provided with at least one flexible substrate, and method of mutually coupling layers' [patent_app_type] => new [patent_app_number] => 10/227229 [patent_app_country] => US [patent_app_date] => 2002-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3127 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20030042563.pdf [firstpage_image] =>[orig_patent_app_number] => 10227229 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/227229
Display device, device provided with at least one flexible substrate, and method of mutually coupling layers Aug 22, 2002 Abandoned
Array ( [id] => 6690895 [patent_doc_number] => 20030038327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Hermetically sealed silicon micro-machined electromechanical system (MEMS) device having diffused conductors' [patent_app_type] => new [patent_app_number] => 10/226518 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4273 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20030038327.pdf [firstpage_image] =>[orig_patent_app_number] => 10226518 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/226518
Hermetically sealed silicon micro-machined electromechanical system (MEMS) device having diffused conductors Aug 21, 2002 Issued
Array ( [id] => 1150086 [patent_doc_number] => 06774450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Semiconductor device with thermoelectric heat dissipating element' [patent_app_type] => B2 [patent_app_number] => 10/225148 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 4900 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774450.pdf [firstpage_image] =>[orig_patent_app_number] => 10225148 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225148
Semiconductor device with thermoelectric heat dissipating element Aug 21, 2002 Issued
Array ( [id] => 7380428 [patent_doc_number] => 20040036171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Method and apparatus for enabling a stitch wire bond in the absence of discrete bump formation, semiconductor device assemblies and electronic systems including same' [patent_app_type] => new [patent_app_number] => 10/225978 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5127 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20040036171.pdf [firstpage_image] =>[orig_patent_app_number] => 10225978 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225978
Method and apparatus for enabling a stitch wire bond in the absence of discrete bump formation, semiconductor device assemblies and electronic systems including same Aug 21, 2002 Abandoned
Array ( [id] => 1132536 [patent_doc_number] => 06787889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Multilevel leadframe for a packaged integrated circuit and method of fabrication' [patent_app_type] => B2 [patent_app_number] => 10/225606 [patent_app_country] => US [patent_app_date] => 2002-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4364 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787889.pdf [firstpage_image] =>[orig_patent_app_number] => 10225606 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/225606
Multilevel leadframe for a packaged integrated circuit and method of fabrication Aug 21, 2002 Issued
Array ( [id] => 6713815 [patent_doc_number] => 20030025163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Semiconductor device having elevated source/drain and method of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/206809 [patent_app_country] => US [patent_app_date] => 2002-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8471 [patent_no_of_claims] => 83 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20030025163.pdf [firstpage_image] =>[orig_patent_app_number] => 10206809 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/206809
Semiconductor device having elevated source/drain Jul 25, 2002 Issued
Array ( [id] => 1264303 [patent_doc_number] => 06660561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-09 [patent_title] => 'Method of assembling a stackable integrated circuit chip' [patent_app_type] => B2 [patent_app_number] => 10/202185 [patent_app_country] => US [patent_app_date] => 2002-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5594 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660561.pdf [firstpage_image] =>[orig_patent_app_number] => 10202185 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/202185
Method of assembling a stackable integrated circuit chip Jul 23, 2002 Issued
Array ( [id] => 7427500 [patent_doc_number] => 20040007749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'ASSEMBLIES DISPLAYING DIFFERENTIAL NEGATIVE RESISTANCE' [patent_app_type] => new [patent_app_number] => 10/193529 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3975 [patent_no_of_claims] => 125 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20040007749.pdf [firstpage_image] =>[orig_patent_app_number] => 10193529 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/193529
Assemblies displaying differential negative resistance Jul 9, 2002 Issued
Array ( [id] => 1302253 [patent_doc_number] => 06624467 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'EEPROM active area castling' [patent_app_type] => B1 [patent_app_number] => 10/193085 [patent_app_country] => US [patent_app_date] => 2002-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4522 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624467.pdf [firstpage_image] =>[orig_patent_app_number] => 10193085 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/193085
EEPROM active area castling Jul 8, 2002 Issued
Array ( [id] => 7427349 [patent_doc_number] => 20040007733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-15 [patent_title] => 'Floating gate memory cell and forming method' [patent_app_type] => new [patent_app_number] => 10/180168 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2527 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20040007733.pdf [firstpage_image] =>[orig_patent_app_number] => 10180168 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/180168
Floating gate memory cell and forming method Jun 25, 2002 Abandoned
Array ( [id] => 6107160 [patent_doc_number] => 20020171112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Non-volatile semiconductor memory device having memory cell array suitable for high density and high integration' [patent_app_type] => new [patent_app_number] => 10/179958 [patent_app_country] => US [patent_app_date] => 2002-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11981 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20020171112.pdf [firstpage_image] =>[orig_patent_app_number] => 10179958 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/179958
Non-volatile semiconductor memory device having memory cell array suitable for high density and high integration Jun 25, 2002 Issued
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