Search

Paul J Killos

Examiner (ID: 6560)

Most Active Art Unit
1206
Art Unit(s)
1623, 1621, 1625, 1206, 1204
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10765124 [patent_doc_number] => 20160111280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/978374 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 21122 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14978374 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/978374
Method for manufacturing semiconductor device Dec 21, 2015 Issued
Array ( [id] => 10765233 [patent_doc_number] => 20160111390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'METHOD FOR MANUFACTURING ELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 14/977211 [patent_app_country] => US [patent_app_date] => 2015-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4778 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14977211 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/977211
METHOD FOR MANUFACTURING ELECTRONIC DEVICES Dec 20, 2015 Abandoned
Array ( [id] => 10765125 [patent_doc_number] => 20160111281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-21 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/972780 [patent_app_country] => US [patent_app_date] => 2015-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12706 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14972780 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/972780
Manufacturing method of semiconductor device Dec 16, 2015 Issued
Array ( [id] => 11911286 [patent_doc_number] => 09780107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Methods of forming integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 14/969709 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2144 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969709 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/969709
Methods of forming integrated circuit devices Dec 14, 2015 Issued
Array ( [id] => 11214936 [patent_doc_number] => 09443977 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-13 [patent_title] => 'FinFET with reduced source and drain resistance' [patent_app_type] => utility [patent_app_number] => 14/967732 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 3814 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967732 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/967732
FinFET with reduced source and drain resistance Dec 13, 2015 Issued
Array ( [id] => 11286680 [patent_doc_number] => 09502540 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-22 [patent_title] => 'Uniform height tall fins with varying silicon germanium concentrations' [patent_app_type] => utility [patent_app_number] => 14/968313 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4279 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968313 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968313
Uniform height tall fins with varying silicon germanium concentrations Dec 13, 2015 Issued
Array ( [id] => 11532523 [patent_doc_number] => 20170092501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'ACTIVATED THIN SILICON LAYERS' [patent_app_type] => utility [patent_app_number] => 14/962093 [patent_app_country] => US [patent_app_date] => 2015-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3087 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14962093 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/962093
ACTIVATED THIN SILICON LAYERS Dec 7, 2015 Abandoned
Array ( [id] => 11671617 [patent_doc_number] => 20170160338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'INTEGRATED CIRCUIT RELIABILITY ASSESSMENT APPARATUS AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/961824 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10218 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961824 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/961824
INTEGRATED CIRCUIT RELIABILITY ASSESSMENT APPARATUS AND METHOD Dec 6, 2015 Abandoned
Array ( [id] => 11666069 [patent_doc_number] => 20170154788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'SiGe FINS FORMED ON A SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/954581 [patent_app_country] => US [patent_app_date] => 2015-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14954581 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/954581
SiGe fins formed on a substrate Nov 29, 2015 Issued
Array ( [id] => 11807167 [patent_doc_number] => 09548250 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-17 [patent_title] => 'Semiconductor device including self-aligned gate structure and improved gate spacer topography' [patent_app_type] => utility [patent_app_number] => 14/951726 [patent_app_country] => US [patent_app_date] => 2015-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6683 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14951726 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/951726
Semiconductor device including self-aligned gate structure and improved gate spacer topography Nov 24, 2015 Issued
Array ( [id] => 11411702 [patent_doc_number] => 09559013 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-31 [patent_title] => 'Stacked nanowire semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/948441 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 44 [patent_no_of_words] => 5524 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948441 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/948441
Stacked nanowire semiconductor device Nov 22, 2015 Issued
Array ( [id] => 14770741 [patent_doc_number] => 10396783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Optical module, manufacturing method thereof and electronic apparatus [patent_app_type] => utility [patent_app_number] => 14/947177 [patent_app_country] => US [patent_app_date] => 2015-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4759 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14947177 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/947177
Optical module, manufacturing method thereof and electronic apparatus Nov 19, 2015 Issued
Array ( [id] => 11957488 [patent_doc_number] => 20170261640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'System And Methods For Cross-Tool Optical Fluid Model Validation And Real-Time Application' [patent_app_type] => utility [patent_app_number] => 15/124282 [patent_app_country] => US [patent_app_date] => 2015-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13287 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15124282 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/124282
System and methods for cross-tool optical fluid model validation and real-time application Nov 18, 2015 Issued
Array ( [id] => 13500017 [patent_doc_number] => 20180301551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => HETEROJUNCTION TFETS EMPLOYING AN OXIDE SEMICONDUCTOR [patent_app_type] => utility [patent_app_number] => 15/768822 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8813 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15768822 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/768822
Heterojunction TFETs employing an oxide semiconductor Nov 15, 2015 Issued
Array ( [id] => 11259438 [patent_doc_number] => 09484342 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-01 [patent_title] => 'Semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 14/938803 [patent_app_country] => US [patent_app_date] => 2015-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14938803 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/938803
Semiconductor apparatus Nov 10, 2015 Issued
Array ( [id] => 10732983 [patent_doc_number] => 20160079133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/933449 [patent_app_country] => US [patent_app_date] => 2015-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2865 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14933449 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/933449
Semiconductor device Nov 4, 2015 Issued
Array ( [id] => 10710026 [patent_doc_number] => 20160056173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'SEMICONDUCTOR DEVICE WITH SURROUNDING GATE TRANSISTORS IN A NAND CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/932175 [patent_app_country] => US [patent_app_date] => 2015-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 59 [patent_no_of_words] => 34771 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14932175 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/932175
SEMICONDUCTOR DEVICE WITH SURROUNDING GATE TRANSISTORS IN A NAND CIRCUIT Nov 3, 2015 Abandoned
Array ( [id] => 10709942 [patent_doc_number] => 20160056089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-25 [patent_title] => 'SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/931012 [patent_app_country] => US [patent_app_date] => 2015-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 12175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14931012 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/931012
Semiconductor device, method of manufacturing the same, and electronic device Nov 2, 2015 Issued
Array ( [id] => 10725773 [patent_doc_number] => 20160071921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/928341 [patent_app_country] => US [patent_app_date] => 2015-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3900 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14928341 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/928341
Semiconductor device and method for manufacturing the same Oct 29, 2015 Issued
Array ( [id] => 10780159 [patent_doc_number] => 20160126315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'III-Nitride Semiconductor Structure with Intermediate and Transition Layers' [patent_app_type] => utility [patent_app_number] => 14/926279 [patent_app_country] => US [patent_app_date] => 2015-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7090 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14926279 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/926279
III-Nitride Semiconductor Structure with Intermediate and Transition Layers Oct 28, 2015 Abandoned
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