Search

Paul J Killos

Examiner (ID: 14937)

Most Active Art Unit
1206
Art Unit(s)
1623, 1621, 1625, 1204, 1206
Total Applications
2978
Issued Applications
2595
Pending Applications
134
Abandoned Applications
247

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1254257 [patent_doc_number] => 06670668 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-30 [patent_title] => 'Microelectronic structure, method for fabricating it and its use in a memory cell' [patent_app_type] => B2 [patent_app_number] => 09/796208 [patent_app_country] => US [patent_app_date] => 2001-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3045 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670668.pdf [firstpage_image] =>[orig_patent_app_number] => 09796208 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/796208
Microelectronic structure, method for fabricating it and its use in a memory cell Feb 27, 2001 Issued
Array ( [id] => 6893083 [patent_doc_number] => 20010015449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-23 [patent_title] => 'Semiconductor - oxide - semiconductor capacitor formed in intergtated circuit' [patent_app_type] => new [patent_app_number] => 09/782409 [patent_app_country] => US [patent_app_date] => 2001-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5793 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20010015449.pdf [firstpage_image] =>[orig_patent_app_number] => 09782409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/782409
Semiconductor - oxide - semiconductor capacitor formed in intergtated circuit Feb 11, 2001 Abandoned
Array ( [id] => 1582917 [patent_doc_number] => 06424001 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Flash memory with ultra thin vertical body transistors' [patent_app_type] => B1 [patent_app_number] => 09/780169 [patent_app_country] => US [patent_app_date] => 2001-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 8988 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424001.pdf [firstpage_image] =>[orig_patent_app_number] => 09780169 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/780169
Flash memory with ultra thin vertical body transistors Feb 8, 2001 Issued
Array ( [id] => 5917990 [patent_doc_number] => 20020113268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Nonvolatile memory, semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/774888 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14626 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20020113268.pdf [firstpage_image] =>[orig_patent_app_number] => 09774888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/774888
Nonvolatile memory, semiconductor device and method of manufacturing the same Jan 31, 2001 Abandoned
Array ( [id] => 6028857 [patent_doc_number] => 20020017715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Method for bonding heatsink to multiple-height chip' [patent_app_type] => new [patent_app_number] => 09/758320 [patent_app_country] => US [patent_app_date] => 2001-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4695 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20020017715.pdf [firstpage_image] =>[orig_patent_app_number] => 09758320 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/758320
Method for bonding heatsink to multiple-height chip Jan 11, 2001 Abandoned
Array ( [id] => 1309938 [patent_doc_number] => 06617638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-09 [patent_title] => 'Tapered floating gate with nitride spacers to prevent reverse tunneling during programming in a split gate flash' [patent_app_type] => B2 [patent_app_number] => 09/755280 [patent_app_country] => US [patent_app_date] => 2001-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3375 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/617/06617638.pdf [firstpage_image] =>[orig_patent_app_number] => 09755280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755280
Tapered floating gate with nitride spacers to prevent reverse tunneling during programming in a split gate flash Jan 7, 2001 Issued
Array ( [id] => 7104781 [patent_doc_number] => 20010004120 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-21 [patent_title] => 'NON-VOLATILE MEMORY CELLS, HIGH VOLTAGE TRANSISTORS AND LOGIC TRANSISTORS INTEGRATED ON A SINGLE CHIP' [patent_app_type] => new-utility [patent_app_number] => 09/746028 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3279 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20010004120.pdf [firstpage_image] =>[orig_patent_app_number] => 09746028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746028
NON-VOLATILE MEMORY CELLS, HIGH VOLTAGE TRANSISTORS AND LOGIC TRANSISTORS INTEGRATED ON A SINGLE CHIP Dec 20, 2000 Abandoned
Array ( [id] => 6123376 [patent_doc_number] => 20020074591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Non-volatile flash memory cell with application of drain induced barrier lowering phenomenon' [patent_app_type] => new [patent_app_number] => 09/739668 [patent_app_country] => US [patent_app_date] => 2000-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20020074591.pdf [firstpage_image] =>[orig_patent_app_number] => 09739668 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739668
Non-volatile flash memory cell with application of drain induced barrier lowering phenomenon Dec 19, 2000 Abandoned
Array ( [id] => 7645697 [patent_doc_number] => 06472272 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Castled active area mask' [patent_app_type] => B1 [patent_app_number] => 09/733850 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4529 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472272.pdf [firstpage_image] =>[orig_patent_app_number] => 09733850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733850
Castled active area mask Dec 7, 2000 Issued
Array ( [id] => 1346862 [patent_doc_number] => 06586776 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Top-emitting and top-illuminated optoelectronic integrated circuit device' [patent_app_type] => B1 [patent_app_number] => 09/724249 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2964 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/586/06586776.pdf [firstpage_image] =>[orig_patent_app_number] => 09724249 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724249
Top-emitting and top-illuminated optoelectronic integrated circuit device Nov 27, 2000 Issued
Array ( [id] => 1132592 [patent_doc_number] => 06787906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Bit line pad and borderless contact on bit line stud with localized etch stop layer formed in an undermined region' [patent_app_type] => B1 [patent_app_number] => 09/699589 [patent_app_country] => US [patent_app_date] => 2000-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4483 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787906.pdf [firstpage_image] =>[orig_patent_app_number] => 09699589 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/699589
Bit line pad and borderless contact on bit line stud with localized etch stop layer formed in an undermined region Oct 29, 2000 Issued
Array ( [id] => 1203442 [patent_doc_number] => 06720606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Dynamic semiconductor memory device having a trench capacitor' [patent_app_type] => B1 [patent_app_number] => 09/660390 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 84 [patent_no_of_words] => 19407 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/720/06720606.pdf [firstpage_image] =>[orig_patent_app_number] => 09660390 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660390
Dynamic semiconductor memory device having a trench capacitor Sep 11, 2000 Issued
Array ( [id] => 1404054 [patent_doc_number] => 06541849 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Memory device power distribution' [patent_app_type] => B1 [patent_app_number] => 09/648880 [patent_app_country] => US [patent_app_date] => 2000-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5866 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541849.pdf [firstpage_image] =>[orig_patent_app_number] => 09648880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/648880
Memory device power distribution Aug 24, 2000 Issued
Array ( [id] => 1196715 [patent_doc_number] => 06727174 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Method for fabricating a dual-diameter electrical conductor' [patent_app_type] => B1 [patent_app_number] => 09/643372 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 26 [patent_no_of_words] => 6190 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727174.pdf [firstpage_image] =>[orig_patent_app_number] => 09643372 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/643372
Method for fabricating a dual-diameter electrical conductor Aug 21, 2000 Issued
Array ( [id] => 1416931 [patent_doc_number] => 06528845 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Non-volatile semiconductor memory cell utilizing trapped charge generated by channel-initiated secondary electron injection' [patent_app_type] => B1 [patent_app_number] => 09/616569 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3560 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528845.pdf [firstpage_image] =>[orig_patent_app_number] => 09616569 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/616569
Non-volatile semiconductor memory cell utilizing trapped charge generated by channel-initiated secondary electron injection Jul 13, 2000 Issued
Array ( [id] => 739032 [patent_doc_number] => 07034402 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-25 [patent_title] => 'Device with segmented ball limiting metallurgy' [patent_app_type] => utility [patent_app_number] => 09/606319 [patent_app_country] => US [patent_app_date] => 2000-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2850 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/034/07034402.pdf [firstpage_image] =>[orig_patent_app_number] => 09606319 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/606319
Device with segmented ball limiting metallurgy Jun 27, 2000 Issued
Array ( [id] => 1480733 [patent_doc_number] => 06452284 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Semiconductor device substrate and a process for altering a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/599419 [patent_app_country] => US [patent_app_date] => 2000-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4628 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452284.pdf [firstpage_image] =>[orig_patent_app_number] => 09599419 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/599419
Semiconductor device substrate and a process for altering a semiconductor device Jun 21, 2000 Issued
09/594989 Mechanically registered and interconnected chip stack Jun 14, 2000 Abandoned
Array ( [id] => 1081330 [patent_doc_number] => 06835979 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-28 [patent_title] => 'Nonvolatle memory' [patent_app_type] => B1 [patent_app_number] => 09/591968 [patent_app_country] => US [patent_app_date] => 2000-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5020 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/835/06835979.pdf [firstpage_image] =>[orig_patent_app_number] => 09591968 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/591968
Nonvolatle memory Jun 11, 2000 Issued
Array ( [id] => 734273 [patent_doc_number] => 07038310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-02 [patent_title] => 'Power module with improved heat dissipation' [patent_app_type] => utility [patent_app_number] => 09/587768 [patent_app_country] => US [patent_app_date] => 2000-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 9495 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038310.pdf [firstpage_image] =>[orig_patent_app_number] => 09587768 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/587768
Power module with improved heat dissipation Jun 5, 2000 Issued
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