Paul J Killos
Examiner (ID: 14937)
Most Active Art Unit | 1206 |
Art Unit(s) | 1623, 1621, 1625, 1204, 1206 |
Total Applications | 2978 |
Issued Applications | 2595 |
Pending Applications | 134 |
Abandoned Applications | 247 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 1395625
[patent_doc_number] => 06548856
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-15
[patent_title] => 'Vertical stacked gate flash memory device'
[patent_app_type] => B1
[patent_app_number] => 09/583403
[patent_app_country] => US
[patent_app_date] => 2000-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 30
[patent_no_of_words] => 3642
[patent_no_of_claims] => 3
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[patent_words_short_claim] => 302
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/548/06548856.pdf
[firstpage_image] =>[orig_patent_app_number] => 09583403
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/583403 | Vertical stacked gate flash memory device | May 30, 2000 | Issued |
Array
(
[id] => 1462399
[patent_doc_number] => 06350627
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-26
[patent_title] => 'Interlevel dielectric thickness monitor for complex semiconductor chips'
[patent_app_type] => B1
[patent_app_number] => 09/548741
[patent_app_country] => US
[patent_app_date] => 2000-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4025
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/350/06350627.pdf
[firstpage_image] =>[orig_patent_app_number] => 09548741
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/548741 | Interlevel dielectric thickness monitor for complex semiconductor chips | Apr 12, 2000 | Issued |
Array
(
[id] => 4356591
[patent_doc_number] => 06174744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-16
[patent_title] => 'Method of producing micro contact structure and contact probe using same'
[patent_app_type] => 1
[patent_app_number] => 9/538117
[patent_app_country] => US
[patent_app_date] => 2000-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 16
[patent_no_of_words] => 4286
[patent_no_of_claims] => 12
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[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/174/06174744.pdf
[firstpage_image] =>[orig_patent_app_number] => 538117
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/538117 | Method of producing micro contact structure and contact probe using same | Mar 28, 2000 | Issued |
Array
(
[id] => 1063776
[patent_doc_number] => 06849949
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-02-01
[patent_title] => 'Thin stacked package'
[patent_app_type] => utility
[patent_app_number] => 09/534648
[patent_app_country] => US
[patent_app_date] => 2000-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 20
[patent_no_of_words] => 5721
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/849/06849949.pdf
[firstpage_image] =>[orig_patent_app_number] => 09534648
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/534648 | Thin stacked package | Mar 22, 2000 | Issued |
Array
(
[id] => 4309897
[patent_doc_number] => 06316293
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Method of forming a nand-type flash memory device having a non-stacked gate transistor structure'
[patent_app_type] => 1
[patent_app_number] => 9/531749
[patent_app_country] => US
[patent_app_date] => 2000-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 38
[patent_no_of_words] => 6674
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/316/06316293.pdf
[firstpage_image] =>[orig_patent_app_number] => 531749
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/531749 | Method of forming a nand-type flash memory device having a non-stacked gate transistor structure | Mar 19, 2000 | Issued |
Array
(
[id] => 1490270
[patent_doc_number] => 06417086
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Method of manufacturing semiconductor device having nonvolatile memory and logic circuit using multi-layered, inorganic mask'
[patent_app_type] => B1
[patent_app_number] => 09/506379
[patent_app_country] => US
[patent_app_date] => 2000-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 38
[patent_no_of_words] => 8710
[patent_no_of_claims] => 11
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/417/06417086.pdf
[firstpage_image] =>[orig_patent_app_number] => 09506379
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/506379 | Method of manufacturing semiconductor device having nonvolatile memory and logic circuit using multi-layered, inorganic mask | Feb 17, 2000 | Issued |
Array
(
[id] => 1452184
[patent_doc_number] => 06455888
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Memory cell structure for elimination of oxynitride (ONO) etch residue and polysilicon stringers'
[patent_app_type] => B1
[patent_app_number] => 09/506298
[patent_app_country] => US
[patent_app_date] => 2000-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 25
[patent_no_of_words] => 6949
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/455/06455888.pdf
[firstpage_image] =>[orig_patent_app_number] => 09506298
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/506298 | Memory cell structure for elimination of oxynitride (ONO) etch residue and polysilicon stringers | Feb 16, 2000 | Issued |
Array
(
[id] => 1386481
[patent_doc_number] => 06555871
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-04-29
[patent_title] => 'Flash memory device having a bipolar transistor formed integral thereto and a method of manufacture therefor'
[patent_app_type] => B1
[patent_app_number] => 09/488108
[patent_app_country] => US
[patent_app_date] => 2000-01-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 13
[patent_no_of_words] => 3792
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 108
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/555/06555871.pdf
[firstpage_image] =>[orig_patent_app_number] => 09488108
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/488108 | Flash memory device having a bipolar transistor formed integral thereto and a method of manufacture therefor | Jan 19, 2000 | Issued |
Array
(
[id] => 949066
[patent_doc_number] => 06963102
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-11-08
[patent_title] => 'Non-volatile semiconductor memory having a decreased gate length'
[patent_app_type] => utility
[patent_app_number] => 09/451619
[patent_app_country] => US
[patent_app_date] => 1999-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 5726
[patent_no_of_claims] => 17
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/963/06963102.pdf
[firstpage_image] =>[orig_patent_app_number] => 09451619
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/451619 | Non-volatile semiconductor memory having a decreased gate length | Nov 29, 1999 | Issued |
Array
(
[id] => 1468507
[patent_doc_number] => 06459118
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-10-01
[patent_title] => 'NAND type nonvolatile ferroelectric memory cell'
[patent_app_type] => B1
[patent_app_number] => 09/433358
[patent_app_country] => US
[patent_app_date] => 1999-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 45
[patent_no_of_words] => 9972
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/459/06459118.pdf
[firstpage_image] =>[orig_patent_app_number] => 09433358
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/433358 | NAND type nonvolatile ferroelectric memory cell | Nov 3, 1999 | Issued |
Array
(
[id] => 1566195
[patent_doc_number] => 06339228
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-01-15
[patent_title] => 'DRAM cell buried strap leakage measurement structure and method'
[patent_app_type] => B1
[patent_app_number] => 09/428598
[patent_app_country] => US
[patent_app_date] => 1999-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 2908
[patent_no_of_claims] => 21
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[patent_words_short_claim] => 139
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/339/06339228.pdf
[firstpage_image] =>[orig_patent_app_number] => 09428598
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/428598 | DRAM cell buried strap leakage measurement structure and method | Oct 26, 1999 | Issued |
Array
(
[id] => 4333096
[patent_doc_number] => 06320202
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Bottom-gated thin film transistors comprising germanium in a channel region'
[patent_app_type] => 1
[patent_app_number] => 9/416561
[patent_app_country] => US
[patent_app_date] => 1999-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/320/06320202.pdf
[firstpage_image] =>[orig_patent_app_number] => 416561
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/416561 | Bottom-gated thin film transistors comprising germanium in a channel region | Oct 11, 1999 | Issued |
Array
(
[id] => 4254375
[patent_doc_number] => 06222223
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Semiconductor device including capacitance element having high area efficiency'
[patent_app_type] => 1
[patent_app_number] => 9/395987
[patent_app_country] => US
[patent_app_date] => 1999-09-15
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[pdf_file] => patents/06/222/06222223.pdf
[firstpage_image] =>[orig_patent_app_number] => 395987
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/395987 | Semiconductor device including capacitance element having high area efficiency | Sep 14, 1999 | Issued |
09/384480 | NON-VOLATILE SEMICONDUCTOR MEMORY CELL UTILIZING SPLIT DIELECTRIC FLOATING GATE | Aug 26, 1999 | Abandoned |
Array
(
[id] => 1561730
[patent_doc_number] => 06437397
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-20
[patent_title] => 'Flash memory cell with vertically oriented channel'
[patent_app_type] => B1
[patent_app_number] => 09/377539
[patent_app_country] => US
[patent_app_date] => 1999-08-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/437/06437397.pdf
[firstpage_image] =>[orig_patent_app_number] => 09377539
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/377539 | Flash memory cell with vertically oriented channel | Aug 18, 1999 | Issued |
Array
(
[id] => 1107686
[patent_doc_number] => 06808996
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-26
[patent_title] => 'Method for protecting gate edges from charge gain/loss in semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/376659
[patent_app_country] => US
[patent_app_date] => 1999-08-18
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[pdf_file] => patents/06/808/06808996.pdf
[firstpage_image] =>[orig_patent_app_number] => 09376659
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/376659 | Method for protecting gate edges from charge gain/loss in semiconductor device | Aug 17, 1999 | Issued |
Array
(
[id] => 6593452
[patent_doc_number] => 20020063249
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-05-30
[patent_title] => 'KERF CONTACT TO SILICON REDESIGN FOR DEFECT ISOLATION AND ANALYSIS'
[patent_app_type] => new
[patent_app_number] => 09/375138
[patent_app_country] => US
[patent_app_date] => 1999-08-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0063/20020063249.pdf
[firstpage_image] =>[orig_patent_app_number] => 09375138
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/375138 | Kerf contact to silicon redesign for defect isolation and analysis | Aug 15, 1999 | Issued |
Array
(
[id] => 1440992
[patent_doc_number] => 06495878
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-17
[patent_title] => 'Interlayer oxide containing thin films for high dielectric constant application'
[patent_app_type] => B1
[patent_app_number] => 09/365628
[patent_app_country] => US
[patent_app_date] => 1999-08-02
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/365628 | Interlayer oxide containing thin films for high dielectric constant application | Aug 1, 1999 | Issued |
Array
(
[id] => 1509309
[patent_doc_number] => 06441427
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-27
[patent_title] => 'NOR-type flash memory and method for manufacturing the same'
[patent_app_type] => B1
[patent_app_number] => 09/364038
[patent_app_country] => US
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[pdf_file] => patents/06/441/06441427.pdf
[firstpage_image] =>[orig_patent_app_number] => 09364038
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/364038 | NOR-type flash memory and method for manufacturing the same | Jul 29, 1999 | Issued |
Array
(
[id] => 1491826
[patent_doc_number] => 06417548
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Variable work function transistor high density mask ROM'
[patent_app_type] => B1
[patent_app_number] => 09/356679
[patent_app_country] => US
[patent_app_date] => 1999-07-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/417/06417548.pdf
[firstpage_image] =>[orig_patent_app_number] => 09356679
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/356679 | Variable work function transistor high density mask ROM | Jul 18, 1999 | Issued |